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31. 发明申请

US20060208693A1 Battery controller 审中-公开
标题翻译：电池控制器
公开(公告)号：US20060208693A1
公开(公告)日：2006-09-21
申请号：US11375073
申请日：2006-03-15
申请人： Akihiko Emori , Youhei Kawahara , Hirotaka Takahashi , Fumio Murabayashi , Tokiyoshi Hirasawa , Tetsuro Okoshi
发明人： Akihiko Emori , Youhei Kawahara , Hirotaka Takahashi , Fumio Murabayashi , Tokiyoshi Hirasawa , Tetsuro Okoshi
IPC分类号： H02J7/00
CPC分类号： H02J7/0047 , G01R31/006 , G01R31/3648 , G01R31/371 , G01R31/379 , G01R31/392
摘要： The aim of the invention is to provide a battery controller which is able to secure the number of rewrite time as required without replacement. The battery controller including a plurality of memory groups 104a to 104n comprising nonvolatile memories rewritable on the basis of one unit or plural units, a switch for selecting a memory group and a reader/writer 102 for writing or reading data into or from the memory groups, wherein the switch selects sequentially a memory group, according to a signal for writing from outside.
摘要翻译：本发明的目的是提供一种电池控制器，其能够在不需要更换的情况下保证所需的重写时间。电池控制器包括多个存储器组104a至104n，包括基于一个单元或多个单元可改写的非易失性存储器，用于选择存储器组的开关和用于将数据写入或读取数据的读取器/写入器102 存储器组，其中所述开关根据从外部写入的信号顺序地选择存储器组。

32. 发明授权

US06999855B2 Vehicle control system and automobile using the same 有权
标题翻译：车辆控制系统和汽车使用相同
公开(公告)号：US06999855B2
公开(公告)日：2006-02-14
申请号：US10428802
申请日：2003-05-05
申请人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
发明人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
IPC分类号： G06F7/00
CPC分类号： B60W50/00 , B60T8/885 , B60T2270/406 , B60W50/0205 , B60W2050/0006 , F02D41/22 , F02D41/266 , F02D41/3005 , F02D2400/18
摘要： A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have a independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.
摘要翻译：低成本车辆控制系统和使用该系统的汽车控制致动器驱动器的辐射，从而降低辐射部件成本，并允许电子控制单元的小型化以提高通用性。车辆控制系统具有电子控制单元，用于在致动器侧驱动致动器的多个致动器和致动器驱动器。致动器驱动器分别具有独立的自诊断部分，自保护部分和通信控制部分，并且相应地分散到致动器。

33. 发明申请

US20060009886A1 Vehicle control system and automobile using the same 有权
公开(公告)号：US20060009886A1
公开(公告)日：2006-01-12
申请号：US11227075
申请日：2005-09-16
申请人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
发明人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
IPC分类号： G06F19/00
CPC分类号： B60W50/00 , B60T8/885 , B60T2270/406 , B60W50/0205 , B60W2050/0006 , F02D41/22 , F02D41/266 , F02D41/3005 , F02D2400/18
摘要： A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.

34. 发明授权

US06657459B2 Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
公开(公告)号：US06657459B2
公开(公告)日：2003-12-02
申请号：US10143762
申请日：2002-05-14
申请人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
发明人： Yoji Nishio , Kosaku Hirose , Hideo Hara , Katsunori Koike , Kayoko Nemoto , Tatsumi Yamauchi , Fumio Murabayashi , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

35. 发明授权

US5931895A Floating-point arithmetic processing apparatus 失效
标题翻译：浮点算术处理装置
公开(公告)号：US5931895A
公开(公告)日：1999-08-03
申请号：US789430
申请日：1997-01-29
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Noriyasu Ido , Yoshikazu Kiyoshige , Takahiro Nishiyama , Eiki Kamada
IPC分类号： G06F7/38 , G06F5/01 , G06F7/00 , G06F7/483 , G06F7/74 , G06F7/76 , G06F7/52
CPC分类号： G06F5/012 , G06F7/483
摘要： A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.
摘要翻译：一种浮点运算处理装置，具有通过从中间结果的指数的值减去归一化数的最小值的指数来生成用于归一化偏移的极限值的电路，以及生成作为归一化的归一化的电路移位数，使中间结果的尾数所需的移位数中的较小的一个是归一化数，以及归一化移位的极限值。浮点运算处理装置还具有电路，该电路具有用于检测在舍入处理之前的溢出条件的电路和用于在溢出的情况下产生值的电路，从而仅当预定值仅在在舍入处理之前检测到溢出条件，但是在另一种情况下，通过执行归一化处理和舍入处理获得的结果被传送。在四舍五入处理之前没有发生溢出，而在舍入处理后发生溢出的情况下，通过执行归一化处理和舍入处理获得的结果作为最终结果被传递。

36. 发明授权

US5869990A Self-timed semiconductor integrated circuit device 失效
标题翻译：自定义半导体集成电路器件
公开(公告)号：US5869990A
公开(公告)日：1999-02-09
申请号：US792799
申请日：1997-02-03
申请人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
发明人： Fumio Murabayashi , Tatsumi Yamauchi , Yutaka Kobayashi
IPC分类号： G06F7/00 , G06F9/38 , G06F15/78 , H04L7/00 , H03K5/13
CPC分类号： G06F9/3869
摘要： A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.
摘要翻译：提供一种半导体集成电路器件，其包括至少一个第一功能电路块，其接收输入信号并执行逻辑运算以输出输出信号。至少一个第二功能电路块与第一功能电路块并联连接。第二功能电路块还响应输入信号以执行逻辑运算并输出输出信号作为结果。第一和第二功能电路块彼此连接，使得第二功能电路块将与第一功能电路块同步操作。更具体地，第一功能电路块被布置成控制第二功能电路块的输出定时。

37. 发明授权

US5377136A Semiconductor integrated circuit device with built-in memory circuit group 失效
标题翻译：具有内置存储电路组的半导体集成电路器件
公开(公告)号：US5377136A
公开(公告)日：1994-12-27
申请号：US076874
申请日：1993-06-15
申请人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
发明人： Yoji Nishio , Fumio Murabayashi , Shoichi Kotoku , Akira Uragami , Manabu Shibata , Yoshitatsu Kojima , Fumiaki Matsuzaki
IPC分类号： G11C5/06 , G11C8/16
CPC分类号： G11C8/16 , G11C5/063
摘要： A semiconductor integrated circuit device with a built-in memory circuit group is disclosed, wherein wiring is started from a data terminal position near a data exchange portion of a memory circuit group to reduce the length of a wiring. Accordingly, an operation speed can be improved by the reduction of wiring capacitance and a ratio of unwired wirings can be reduced by reduction of an occupying ratio of wiring channels.
摘要翻译：公开了一种具有内置存储器电路组的半导体集成电路器件，其中从存储器电路组的数据交换部分附近的数据终端位置开始布线以减少布线的长度。因此，可以通过减少布线电容来提高操作速度，并且可以通过降低布线通道的占有率来减少退绕布线的比率。

38. 发明授权

US06798255B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06798255B2
公开(公告)日：2004-09-28
申请号：US09931250
申请日：2001-08-17
申请人： Fumikazu Takahashi , Tatsumi Yamauchi , Fumio Murabayashi , Kazuhisa Miyamoto , Kazuharu Kuchimachi
发明人： Fumikazu Takahashi , Tatsumi Yamauchi , Fumio Murabayashi , Kazuhisa Miyamoto , Kazuharu Kuchimachi
IPC分类号： H03B2100
CPC分类号： H03K5/15013
摘要： A semiconductor integrated circuit device including a driver circuit, a first long-distance wiring connected to the driver circuit, and a plurality of gate circuits connected over the entire length of the first long-distance wiring, so that an output signal of the driver circuit is received by the plurality of gate circuits via the first long-distance wiring, wherein a node arranged in the vicinity of an input terminal of the gate circuit connected to an input terminal of the driver circuit and an end of the first long-distance wiring is connected by a second long-distance wiring and a speed-increasing circuit.
摘要翻译：一种半导体集成电路装置，包括驱动电路，连接到驱动电路的第一长距离布线和连接在第一长距离布线的整个长度上的多个门电路，使得驱动电路的输出信号经由第一长距离布线由多个门电路接收，其中布置在连接到驱动电路的输入端的门电路的输入端附近的节点和第一长距离布线的端部通过第二长距离布线和增速电路连接。

39. 发明授权

US06625522B2 Vehicle control system and automobile using the same 失效
标题翻译：车辆控制系统和汽车使用相同
公开(公告)号：US06625522B2
公开(公告)日：2003-09-23
申请号：US09801656
申请日：2001-03-09
申请人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
发明人： Kohei Sakurai , Nobuyasu Kanekawa , Fumio Murabayashi , Mitsuru Watabe , Toshio Hayashibara
IPC分类号： G06F700
CPC分类号： B60W50/00 , B60T8/885 , B60T2270/406 , B60W50/0205 , B60W2050/0006 , F02D41/22 , F02D41/266 , F02D41/3005 , F02D2400/18
摘要： A low-cost vehicle control system and a car using the system controls radiation of an actuator driver and thereby reduces the radiation component cost and allows downsizing of an electronic control unit to improve the versatility. The vehicle control system has an electronic control unit, a plurality of actuators and actuator drivers for driving the actuators at the actuator side. The actuator drivers, respectively, have an independent self-diagnosis section, a self-protection section, and a communication control section and are dispersed correspondingly to the actuators.
摘要翻译：低成本车辆控制系统和使用该系统的汽车控制致动器驱动器的辐射，从而降低辐射部件成本，并允许电子控制单元的小型化以提高通用性。车辆控制系统具有电子控制单元，用于在致动器侧驱动致动器的多个致动器和致动器驱动器。执行器驱动器分别具有独立的自诊断部分，自保护部分和通信控制部分，并且相应地分散到致动器。

40. 发明授权

US06590425B2 Semiconductor integrated circuit apparatus 失效
标题翻译：半导体集成电路装置
公开(公告)号：US06590425B2
公开(公告)日：2003-07-08
申请号：US09887065
申请日：2001-06-25
申请人： Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hiromichi Yamada
发明人： Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hiromichi Yamada
IPC分类号： H03K19096
CPC分类号： H03K19/00338
摘要： There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented. There is also disclosed a parallel data processing apparatus which features such logic circuitry, the data processing apparatus having both a plurality of data processing units, each having a processor and a memory, and a plurality of hard disks.
摘要翻译：公开了一种电路装置，其高度耐受噪声并以比传统的完全互补的静态CMOS电路更高的速度工作。为了实现这一点，电路装置具有串联连接的多个CMOS静态逻辑电路和连接到这些逻辑电路的输出部分的电位设置电路，并将输出部分的输出与时钟信号，从而通过NMOS电路的操作传播信号。换句话说，信号传播延迟仅在N型逻辑块导通时才发生。因此，可以防止电路操作加剧，并且可以防止由于电荷再分配效应或漏电流引起的α粒子噪声和噪声。还公开了一种具有这种逻辑电路的并行数据处理装置，数据处理装置具有多个数据处理单元，每个数据处理单元具有处理器和存储器，以及多个硬盘。

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