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31. 发明申请

US20070260848A1 Power mangement integrated circuit 有权
标题翻译：电力管理集成电路
公开(公告)号：US20070260848A1
公开(公告)日：2007-11-08
申请号：US11825252
申请日：2007-07-03
申请人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Howard Wilson , Donald Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek De , Shekhar Borkar
IPC分类号： G06F15/00 , H01L21/50 , H01L23/34
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

32. 发明申请

US20070168848A1 Error-detection flip-flop 有权
标题翻译：错误检测触发器
公开(公告)号：US20070168848A1
公开(公告)日：2007-07-19
申请号：US11323675
申请日：2005-12-30
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： G06F11/00
CPC分类号： G01R31/31937 , G01R31/31726
摘要： An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
摘要翻译：公开了用于识别数字电路中的定时误差的错误检测触发器。误差检测触发器是主从触发器，其包括用于确定在预定时钟周期期间是否接收到输入信号的逻辑，表示定时误差。误差检测触发器产生可变长度误差脉冲，其可以与其他误差脉冲组合并转换成用于由纠错电路进行采样的稳定信号。误差检测触发器不会增加数字电路的时钟功率，并且消耗少量额外的电路面积。

33. 发明申请

US20070164371A1 Reliability degradation compensation using body bias 审中-公开
标题翻译：使用身体偏倚的可靠性退化补偿
公开(公告)号：US20070164371A1
公开(公告)日：2007-07-19
申请号：US11321100
申请日：2005-12-29
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： H01L29/76
CPC分类号： G01R31/2642
摘要： A system may include detection of reliability degradation of a transistor, and change of a body bias applied to the transistor based on the detected reliability degradation.
摘要翻译：系统可以包括基于检测到的可靠性降级来检测晶体管的可靠性劣化以及施加到晶体管的体偏置的变化。

34. 发明申请

US20060259890A1 Method and apparatus for power consumption reduction 失效
标题翻译：降低功耗的方法和装置
公开(公告)号：US20060259890A1
公开(公告)日：2006-11-16
申请号：US11486030
申请日：2006-07-14
申请人： James Tschanz , Nasser Kurd , Javed Barkatullah , Vivek De
发明人： James Tschanz , Nasser Kurd , Javed Barkatullah , Vivek De
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
摘要翻译：提供了一种降低功耗的方法和芯片设计。具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。第二功能块内的边沿触发电路可以用双边沿触发电路代替。相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

35. 发明申请

US20060226863A1 Method and apparatus to adjust die frequency 审中-公开
标题翻译：调整芯片频率的方法和装置
公开(公告)号：US20060226863A1
公开(公告)日：2006-10-12
申请号：US11094574
申请日：2005-03-31
申请人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Tawfik Arabi , Grant McFarland , Vivek De
发明人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Tawfik Arabi , Grant McFarland , Vivek De
IPC分类号： G01R31/26
CPC分类号： G01R31/2882 , G01R31/2879
摘要： A method and apparatus are provided for adjusting a frequency of a die. This may include measuring characteristics of a die at various combinations of power supply voltage, body bias voltage and/or temperature and determining operating characteristics, such as power supply voltage and body bias voltage, based on the measured characteristics.
摘要翻译：提供了一种用于调整管芯频率的方法和装置。这可以包括基于所测量的特性，在电源电压，体偏置电压和/或温度的各种组合下测量管芯的特性，并确定诸如电源电压和体偏置电压的操作特性。

36. 发明申请

US20060132218A1 Body biasing methods and circuits 审中-公开
标题翻译：车身偏置方式和电路
公开(公告)号：US20060132218A1
公开(公告)日：2006-06-22
申请号：US11018016
申请日：2004-12-20
申请人： James Tschanz , Siva Narendra , Vivek De
发明人： James Tschanz , Siva Narendra , Vivek De
IPC分类号： H03K3/01
CPC分类号： G05F3/205 , H03K2217/0018
摘要： In some embodiments, a chip is provided that comprises a group of transistors and a body bias generator. The group of transistors is coupled to the body bias generator. The body bias generator is configured to body bias the transistors at a level based on one or more measured parameters associated with the chip and on an operating mode. Other embodiments are disclosed herein and/or are otherwise claimed.
摘要翻译：在一些实施例中，提供了包括一组晶体管和体偏置发生器的芯片。晶体管组耦合到体偏置发生器。身体偏置发生器被配置为基于与芯片相关联的一个或多个测量参数和在操作模式上将晶体管偏置在一个电平上。其他实施方案在此公开和/或以其他方式要求保护。

37. 发明授权

US09455011B2 Methods and systems to read a magnetic tunnel junction (MTJ) based memory cell based on a pulsed read current 有权
标题翻译：基于脉冲读取电流读取基于磁隧道结（MTJ）的存储单元的方法和系统
公开(公告)号：US09455011B2
公开(公告)日：2016-09-27
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/00 , G11C11/16 , G11C5/12 , G11C13/00
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

38. 发明授权

US08589706B2 Data inversion based approaches for reducing memory power consumption 有权
标题翻译：用于减少内存功耗的基于数据反演的方法
公开(公告)号：US08589706B2
公开(公告)日：2013-11-19
申请号：US11964551
申请日：2007-12-26
申请人： Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
发明人： Ming Zhang , Chris Wilkerson , Greg Taylor , Randy J. Aksamit , James Tschanz
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3293 , G06F12/0802 , G06F2212/1028 , Y02D10/13
摘要： Disclosed herein are approaches to reducing a guardband (margin) used for minimum voltage supply (Vcc) requirements for memory such as cache.
摘要翻译：这里公开了减少用于诸如高速缓存的存储器的最小电压供应（Vcc）要求的保护带（余量）的方法。

39. 发明申请

US20150206564A1 METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED MEMORY CELL BASED ON A PULSED READ CURRENT 有权
标题翻译：基于脉冲读取电流读取基于磁悬浮连接（MTJ）的存储单元的方法和系统
公开(公告)号：US20150206564A1
公开(公告)日：2015-07-23
申请号：US14350997
申请日：2012-03-25
申请人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
发明人： Arijit Raychowdhury , David Kencke , Brian Doyle , Charles Kuo , James Tschanz , Fatih Hamzaoglu , Yih Wang , Roksana Golizadeh Mojarad
IPC分类号： G11C11/16 , G11C5/12
CPC分类号： G11C11/165 , G11C5/12 , G11C11/1673 , G11C11/1693 , G11C2013/0052 , G11C2013/0071
摘要： Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.
摘要翻译：基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列在BL上。可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。预充电的BL电容也可以用作电压积分器。

40. 发明授权

US09299395B2 Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks 有权
标题翻译：选择性地提高8T位单元阵列和/或其他逻辑块的工作电压并控制其的方法和系统
公开(公告)号：US09299395B2
公开(公告)日：2016-03-29
申请号：US14350546
申请日：2012-03-26
申请人： Jaydeep P. Kulkarni , Bibiche M. Geuskens , James Tschanz , Vivek K. De , Muhammad M. Khellah
发明人： Jaydeep P. Kulkarni , Bibiche M. Geuskens , James Tschanz , Vivek K. De , Muhammad M. Khellah
IPC分类号： G11C11/419 , G11C5/14 , G11C7/08 , G11C11/4074 , G11C11/417 , G11C7/12 , G11C8/10 , G11C11/418 , G11C13/00 , G11C29/02 , G11C11/412
CPC分类号： G11C11/419 , G11C5/14 , G11C5/145 , G11C5/147 , G11C5/148 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C2207/2227
摘要： Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
摘要翻译：提供多Vcc环境的方法和系统，例如选择性地提高逻辑块的工作电压和/或向逻辑块提供电平移位控制。可以实现多Vcc环境以将Vmin限制逻辑块与单Vcc环境隔离，例如在单Vcc环境中减少Vmin和/或提高能量效率。逻辑块可以包括寄存器文件的位单元，低级处理器高速缓存和/或其他存储器系统。可以在读取模式期间升高单元Vcc，和/或写入字线（WWL）和/或读取字线（RWL）可以通过升压来断言。字线解码器可以包括具有差分分离级逻辑的电压电平移位器和动态NAND，其可以包括NAND逻辑，保持器电路和用于基于电平移位器的延迟来延迟保持器控制的逻辑，以减少在初始NAND评估阶段。

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