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1. 发明授权

US07409631B2 Error-detection flip-flop 有权
标题翻译：错误检测触发器
公开(公告)号：US07409631B2
公开(公告)日：2008-08-05
申请号：US11323675
申请日：2005-12-30
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G01R31/31937 , G01R31/31726
摘要： An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
摘要翻译：公开了用于识别数字电路中的定时误差的错误检测触发器。误差检测触发器是主从触发器，其包括用于确定在预定时钟周期期间是否接收到输入信号的逻辑，表示定时误差。误差检测触发器产生可变长度误差脉冲，其可以与其他误差脉冲组合并转换成用于由纠错电路进行采样的稳定信号。误差检测触发器不会增加数字电路的时钟功率，并且消耗少量额外的电路面积。

2. 发明申请

US20070168848A1 Error-detection flip-flop 有权
标题翻译：错误检测触发器
公开(公告)号：US20070168848A1
公开(公告)日：2007-07-19
申请号：US11323675
申请日：2005-12-30
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： G06F11/00
CPC分类号： G01R31/31937 , G01R31/31726
摘要： An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
摘要翻译：公开了用于识别数字电路中的定时误差的错误检测触发器。误差检测触发器是主从触发器，其包括用于确定在预定时钟周期期间是否接收到输入信号的逻辑，表示定时误差。误差检测触发器产生可变长度误差脉冲，其可以与其他误差脉冲组合并转换成用于由纠错电路进行采样的稳定信号。误差检测触发器不会增加数字电路的时钟功率，并且消耗少量额外的电路面积。

3. 发明申请

US20070164371A1 Reliability degradation compensation using body bias 审中-公开
标题翻译：使用身体偏倚的可靠性退化补偿
公开(公告)号：US20070164371A1
公开(公告)日：2007-07-19
申请号：US11321100
申请日：2005-12-29
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： H01L29/76
CPC分类号： G01R31/2642
摘要： A system may include detection of reliability degradation of a transistor, and change of a body bias applied to the transistor based on the detected reliability degradation.
摘要翻译：系统可以包括基于检测到的可靠性降级来检测晶体管的可靠性劣化以及施加到晶体管的体偏置的变化。

4. 发明授权

US09748421B2 Multiple carbon nanotube transfer and its applications for making high-performance carbon nanotube field-effect transistor (CNFET), transparent electrodes, and three-dimensional integration of CNFETs 有权
公开(公告)号：US09748421B2
公开(公告)日：2017-08-29
申请号：US12718418
申请日：2010-03-05
申请人： Subhasish Mitra , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
发明人： Subhasish Mitra , Nishant P. Patil , Chung Chun Wan , H.-S. Philip Wong
IPC分类号： H01L31/0352 , B08B7/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L51/00 , H01L27/28 , H01L51/05
CPC分类号： H01L31/035281 , B08B7/0035 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L27/283 , H01L51/0013 , H01L51/003 , H01L51/0048 , H01L51/0541 , H01L51/0558 , Y02E10/549 , Y02P70/521
摘要： A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications. Further, three-dimensional CNFETs can be provided by utilizing the subject plasma exposure processes.

5. 发明申请

US20060168489A1 System and shadow circuits with output joining circuit 有权
标题翻译：具有输出接合电路的系统和阴影电路
公开(公告)号：US20060168489A1
公开(公告)日：2006-07-27
申请号：US11044826
申请日：2005-01-26
申请人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
发明人： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318541
摘要： In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
摘要翻译：在一个实施例中，一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路，其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。

6. 发明申请

US20060168487A1 System pulse latch and shadow pulse latch coupled to output joining circuit 有权
标题翻译：系统脉冲锁存和阴影脉冲锁存器耦合到输出接合电路
公开(公告)号：US20060168487A1
公开(公告)日：2006-07-27
申请号：US11128692
申请日：2005-05-12
申请人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
发明人： Tak Mak , Ming Zhang , Subhasish Mitra , Paul Shipley
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： H03K3/356156 , G01R31/318583 , H03K3/0375
摘要： In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
摘要翻译：在一个实施例中，一种装置包括系统脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个系统锁存信号; 阴影脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个阴影锁存信号; 以及耦合到系统脉冲锁存器和阴影脉冲锁存器的输出连接电路，以响应于至少一个系统锁存信号和至少一个阴影锁存信号来提供数据输出信号。

7. 发明授权

US07911234B1 Nanotube logic circuits 有权
标题翻译：纳米管逻辑电路
公开(公告)号：US07911234B1
公开(公告)日：2011-03-22
申请号：US12240365
申请日：2008-09-29
申请人： Nishant Patil , Subhasish Mitra
发明人： Nishant Patil , Subhasish Mitra
IPC分类号： H03K19/20
CPC分类号： B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558
摘要： A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.
摘要翻译：对不对称的碳纳米管免疫的逻辑电池。碳纳米管位于基底上。触点形成在碳纳米管层上，包括第一输入触点，第二输入触点，输出触点，第一栅极区和第二栅极区。输出触点位于第一输入触点和第二输入触点之间，并且单元区域由输出触点的宽度限定并且位于第一输入触点和第二输入触点之间。非导电区域位于多个触点中的任何两个或更多个触点之间的碳纳米管层中，如果短路，则阻止逻辑功能。

8. 发明授权

US07574640B2 Compacting circuit responses 有权
标题翻译：压缩电路响应
公开(公告)号：US07574640B2
公开(公告)日：2009-08-11
申请号：US10656013
申请日：2003-09-05
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.
摘要翻译：压实机具有减少的输出数量和处理更多数量的错误和未知逻辑值的能力。设计矩阵和产生的压实机的过程涉及确定可能遇到的未知逻辑值的数量，并且基于错误数量向压实器矩阵添加列。基本上，确定线中扫描的可能组合的数量。然后，为行中扫描的每种可能组合添加其他列。为行中的扫描的每个组合添加的列数等于错误数量加上一个实施例中的列数。

9. 发明授权

US07373572B2 System pulse latch and shadow pulse latch coupled to output joining circuit 有权
标题翻译：系统脉冲锁存和阴影脉冲锁存器耦合到输出接合电路
公开(公告)号：US07373572B2
公开(公告)日：2008-05-13
申请号：US11128692
申请日：2005-05-12
申请人： Tak M. Mak , Ming Zhang , Subhasish Mitra , Paul E. Shipley
发明人： Tak M. Mak , Ming Zhang , Subhasish Mitra , Paul E. Shipley
IPC分类号： G01R31/28
CPC分类号： H03K3/356156 , G01R31/318583 , H03K3/0375
摘要： In one embodiment, an apparatus includes a system pulse latch to generate at least one system latch signal in response to a data input signal and a pulsed system clock signal; a shadow pulse latch to generate at least one shadow latch signal in response to the data input signal and the pulsed system clock signal; and an output joining circuit, coupled to the system pulse latch and the shadow pulse latch, to provide a data output signal in response to the at least one system latch signal and the at least one shadow latch signal.
摘要翻译：在一个实施例中，一种装置包括系统脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个系统锁存信号; 阴影脉冲锁存器，用于响应于数据输入信号和脉冲系统时钟信号而产生至少一个阴影锁存信号; 以及耦合到系统脉冲锁存器和阴影脉冲锁存器的输出连接电路，以响应于至少一个系统锁存信号和至少一个阴影锁存信号来提供数据输出信号。

10. 发明授权

US07240260B2 Stimulus generation 有权
标题翻译：刺激生成
公开(公告)号：US07240260B2
公开(公告)日：2007-07-03
申请号：US10317605
申请日：2002-12-11
申请人： Subhasish Mitra , Kee Sup Kim
发明人： Subhasish Mitra , Kee Sup Kim
IPC分类号： G01R31/3183 , G01R31/316
CPC分类号： G01R31/318547
摘要： In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.
摘要翻译：在一个实施例中，提供了一种方法。在本实施例的方法中，可以产生刺激信号组并作为输入提供给第一电路。可以至少部分地基于输入信号组的相应非零子集来生成刺激信号组中的各个刺激信号。基于输入信号组的相同的非零子集，可以在刺激信号组中不产生两个相应的刺激信号。刺激信号组可以包括大于输入信号组中相应数量的输入信号的相应数量的激励信号。当然，在不脱离本实施例的方法的情况下，可以进行许多修改，变化和替代。

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