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31. 发明授权

US06855583B1 Method for forming tri-gate FinFET with mesa isolation 失效
标题翻译：用于形成台栅隔离的三栅极FinFET的方法
公开(公告)号：US06855583B1
公开(公告)日：2005-02-15
申请号：US10633503
申请日：2003-08-05
申请人： Zoran Krivokapic , Judy Xilin An , Bin Yu
发明人： Zoran Krivokapic , Judy Xilin An , Bin Yu
IPC分类号： H01L21/336 , H01L29/786 , H01L21/00
CPC分类号： H01L29/785 , H01L29/66545 , H01L29/66795
摘要： A method forming a tri-gate fin field effect transistor includes forming an oxide layer over a silicon-on-insulator wafer comprising a silicon layer, and etching the silicon and oxide layers using a rectangular mask to form a mesa. The method further includes etching a portion of the mesa using a second mask to form a fin, forming a gate dielectric layer over the fin, and forming a tri-gate over the fin and the gate dielectric layer.
摘要翻译：形成三栅极鳍场效应晶体管的方法包括在包括硅层的绝缘体上硅晶片上形成氧化物层，并且使用矩形掩模蚀刻硅和氧化物层以形成台面。该方法还包括使用第二掩模蚀刻台面的一部分以形成翅片，在翅片上形成栅极电介质层，并在鳍状物和栅极介电层上形成三栅极。

32. 发明授权

US06555879B1 SOI device with metal source/drain and method of fabrication 有权
标题翻译：具有金属源/漏极的SOI器件及其制造方法
公开(公告)号：US06555879B1
公开(公告)日：2003-04-29
申请号：US10044247
申请日：2002-01-11
申请人： Zoran Krivokapic , Qi Xiang , Bin Yu
发明人： Zoran Krivokapic , Qi Xiang , Bin Yu
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A MOSFET and method of fabrication. The MOSFET includes a metal containing source and a metal containing drain; a semiconductor body having a thickness of less than about 15 nm disposed between the source and the drain and on top of an insulating layer, the insulating layer formed on a substrate; a gate electrode disposed over the body and defining a channel interposed between the source and the drain; and a gate dielectric made from a high-K material and separating the gate electrode and the body.
摘要翻译：一种MOSFET及其制造方法。 MOSFET包括含金属源和含金属的漏极; 设置在源极和漏极之间并且在绝缘层的顶部上具有小于约15nm的厚度的半导体本体，所述绝缘层形成在基板上; 栅电极，其设置在所述主体上并且限定插入在所述源极和所述漏极之间的沟道; 以及由高K材料制成并分离栅电极和主体的栅极电介质。

33. 发明授权

US06717212B2 Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure 有权
标题翻译：绝缘体上绝缘体（SOI）结构中的漏电导热绝缘体材料（LTCIM）
公开(公告)号：US06717212B2
公开(公告)日：2004-04-06
申请号：US09879724
申请日：2001-06-12
申请人： Dong-Hyuk Ju , William George En , Srinath Krishnan , Concetta E. Riccobene , Zoran Krivokapic , Judy Xilin An , Bin Yu
发明人： Dong-Hyuk Ju , William George En , Srinath Krishnan , Concetta E. Riccobene , Zoran Krivokapic , Judy Xilin An , Bin Yu
IPC分类号： H01L31392
CPC分类号： H01L21/76254 , H01L21/187 , H01L29/78603 , H01L29/78606 , H01L29/78609 , H01L29/78612
摘要： A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.
摘要翻译：一种用于制造绝缘体半导体（SOI）结构的装置和方法，其具有设置在半导体衬底和半导体层之间的具有泄漏的导热材料（LTCIM）层。

34. 发明申请

US20140015015A1 FINFET DEVICE WITH A GRAPHENE GATE ELECTRODE AND METHODS OF FORMING SAME 有权
标题翻译：具有石墨烯电极的FINFET器件及其形成方法
公开(公告)号：US20140015015A1
公开(公告)日：2014-01-16
申请号：US13545621
申请日：2012-07-10
申请人： Zoran Krivokapic , Bhagawan Sahu
发明人： Zoran Krivokapic , Bhagawan Sahu
IPC分类号： H01L21/20 , H01L29/78
CPC分类号： H01L29/51 , H01L21/02527 , H01L21/0262 , H01L21/02628 , H01L21/02664 , H01L29/4966 , H01L29/785
摘要： One illustrative device disclosed herein includes at least one fin comprised of a semiconducting material, a layer of gate insulation material positioned adjacent an outer surface of the fin, a gate electrode comprised of graphene positioned on the layer of gate insulation material around at least a portion of the fin, and an insulating material formed on the gate electrode.
摘要翻译：本文公开的一个说明性装置包括至少一个由半导体材料构成的鳍片，邻近翅片的外表面定位的栅极绝缘材料层，由石墨烯组成的栅电极，栅极电极定位在栅极绝缘材料层周围的至少一部分并且形成在栅电极上的绝缘材料。

35. 发明授权

US08102000B2 P-channel germanium on insulator (GOI) one transistor memory cell 有权
标题翻译：绝缘体上的P沟道锗（GOI）一个晶体管存储单元
公开(公告)号：US08102000B2
公开(公告)日：2012-01-24
申请号：US12082637
申请日：2008-04-10
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L29/49
CPC分类号： H01L29/78684 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841 , H01L29/7842
摘要： According to one exemplary embodiment, a p-channel germanium on insulator (GOI) one transistor memory cell comprises a buried oxide (BOX) layer formed over a bulk substrate, and a gate formed over a gate dielectric layer situated over a germanium layer formed over the buried oxide (BOX) layer. A source region is formed in the germanium layer adjacent to a channel region underlying the gate and overlaying the BOX layer, and a drain region is formed in the germanium layer adjacent to the channel region. The source region and the drain region are implanted with a p-type dopant. In one embodiment, a p-channel GOI one transistor memory cell is implemented as a capacitorless dynamic random access memory (DRAM) cell. In one embodiment, a plurality of p-channel GOI one transistor memory cells are included in a memory array.
摘要翻译：根据一个示例性实施例，绝缘体上的p沟道锗（GOI）一个晶体管存储单元包括在体衬底上形成的掩埋氧化物（BOX）层，以及形成在位于锗层上方的栅介质层上的栅极掩埋氧化物（BOX）层。源极区域形成在与栅极下方的沟道区相邻的锗层中，并覆盖BOX层，并且在与沟道区相邻的锗层中形成漏极区。源极区和漏极区注入p型掺杂剂。在一个实施例中，p沟道GOI一晶体管存储单元被实现为无电容动态随机存取存储器（DRAM）单元。在一个实施例中，多个p沟道GOI一个晶体管存储单元包括在存储器阵列中。

36. 发明申请

US20100051960A1 DEVICE AND PROCESS OF FORMING DEVICE WITH PRE-PATTERNED TRENCH AND GRAPHENE-BASED DEVICE STRUCTURE FORMED THEREIN 有权
标题翻译：具有预先形成的TRENCH和基于石墨的器件结构形成器件的器件和工艺
公开(公告)号：US20100051960A1
公开(公告)日：2010-03-04
申请号：US12201851
申请日：2008-08-29
申请人： An Chen , Zoran Krivokapic
发明人： An Chen , Zoran Krivokapic
IPC分类号： H01L29/16 , H01L21/04
CPC分类号： H01L29/78684 , H01L29/1606 , H01L29/66742 , H01L29/7781
摘要： A graphene-based device is formed with a trench in one or more layers of material, a graphene layer within the trench, and a device structure on the graphene layer and within the trench. Fabrication techniques includes forming a trench defined by one or more layers of material, forming a graphene layer within the trench, and forming a device structure on the graphene layer and within the trench.
摘要翻译：基于石墨烯的器件形成有一层或多层材料中的沟槽，沟槽内的石墨烯层，以及石墨烯层和沟槽内的器件结构。制造技术包括形成由一层或多层材料限定的沟槽，在沟槽内形成石墨烯层，并在石墨烯层和沟槽内形成器件结构。

37. 发明授权

US07202118B1 Fully depleted SOI MOSFET arrangement with sunken source/drain regions 有权
标题翻译：具有凹陷源极/漏极区域的完全耗尽的SOI MOSFET布置
公开(公告)号：US07202118B1
公开(公告)日：2007-04-10
申请号：US10460402
申请日：2003-06-13
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/66636 , H01L29/66772
摘要： A fully depleted SOI MOSFET arrangement includes a buried oxide (BOX) layer with recesses in the BOX layer and a post extended upwardly between the recesses. A thin channel region is formed on the post and a gate over the channel. Deep source/drain region are adjacent to the channel region and extend into the recesses.
摘要翻译：完全耗尽的SOI MOSFET布置包括在BOX层中具有凹陷的掩埋氧化物（BOX）层和在凹部之间向上延伸的柱。在通道上形成了一个薄的通道区域和一个栅极。深源极/漏极区域与沟道区域相邻并延伸到凹槽中。

38. 发明授权

US06975014B1 Method for making an ultra thin FDSOI device with improved short-channel performance 有权
标题翻译：制造具有改进的短通道性能的超薄FDSOI器件的方法
公开(公告)号：US06975014B1
公开(公告)日：2005-12-13
申请号：US09826634
申请日：2001-04-05
申请人： Zoran Krivokapic , Sunny Cherian , Allison Holbrook
发明人： Zoran Krivokapic , Sunny Cherian , Allison Holbrook
IPC分类号： H01L21/336 , H01L29/00 , H01L29/423 , H01L29/786
CPC分类号： H01L29/78696 , H01L29/42384 , H01L29/66545 , H01L29/66772 , H01L29/78621
摘要： A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.
摘要翻译：用于形成通道长度小于50nm并具有良好的短通道控制的FDSOI器件的方法。栅极具有锥形多晶硅间隔物和电介质间隔物。形成多晶硅栅极特征，并在其上形成电介质侧壁间隔物。然后蚀刻多晶硅栅极特征以形成由间隙分开的锥形多晶硅特征。在低温下沉积栅极电介质，然后将金属沉积到间隙中以形成金属栅极。

39. 发明授权

US06917068B1 Semiconductor device having conductive structures formed near a gate electrode 有权
标题翻译：具有形成在栅电极附近的导电结构的半导体器件
公开(公告)号：US06917068B1
公开(公告)日：2005-07-12
申请号：US10454517
申请日：2003-06-05
申请人： Zoran Krivokapic
发明人： Zoran Krivokapic
IPC分类号： H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786 , H01L29/788 , H01L29/76
CPC分类号： H01L29/42332 , H01L21/28273 , H01L27/115 , H01L29/42384 , H01L29/4983 , H01L29/7831 , H01L29/78645 , H01L29/7883
摘要： A semiconductor device is provided by forming a gate electrode and a dielectric layer below and adjacent the side surfaces of the gate electrode. Relatively thin conductive structures are formed within the dielectric layer. The conductive structures may be used as a floating gate electrode for a memory device. The conductive structures may also be used to control a threshold voltage for a logic device.
摘要翻译：通过在栅电极的侧表面下方和邻近形成栅电极和电介质层来提供半导体器件。在介电层内形成相对较薄的导电结构。导电结构可以用作存储器件的浮栅电极。导电结构也可用于控制逻辑器件的阈值电压。

40. 发明授权

US06861307B2 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06861307B2
公开(公告)日：2005-03-01
申请号：US10631199
申请日：2003-07-31
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/28 , H01L29/51 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

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