专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07691727B2 Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors 有权
标题翻译：用于制造具有完全耗尽和部分耗尽的晶体管的集成电路的方法
公开(公告)号：US07691727B2
公开(公告)日：2010-04-06
申请号：US11846622
申请日：2007-08-29
申请人： Philippe Coronel , Michel Marty
发明人： Philippe Coronel , Michel Marty
IPC分类号： H01L21/00
CPC分类号： H01L21/84
摘要： A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.
摘要翻译：一种用于制造包含完全和部分耗尽的MOS晶体管的集成电路的方法，包括以下步骤：在沉积在硅衬底上的硅 - 锗层上形成的薄硅层上形成类似的MOS晶体管; 将所述结构的上表面附接到支撑晶片; 消除基板; 在完全耗尽的晶体管的位置处沉积掩模并打开该掩模; 在发生冷凝现象的条件下，在完全耗尽的晶体管的位置氧化硅 - 锗; 并且消除氧化部分和硅 - 锗部分，由此保留具有薄化硅层的晶体管。

32. 发明授权

US07038289B2 Deep insulating trench 有权
标题翻译：深绝缘沟槽
公开(公告)号：US07038289B2
公开(公告)日：2006-05-02
申请号：US10479639
申请日：2002-06-13
申请人： Michel Marty , Arnoud Fortuin , Vincent Arnal
发明人： Michel Marty , Arnoud Fortuin , Vincent Arnal
IPC分类号： H01L29/00
CPC分类号： H01L21/76232 , H01L21/31612 , H01L21/76237 , H01L21/764
摘要： Deep isolation trenches having sides and a bottom are formed in a semiconductor substrate. The sides and the bottom are coated with an electrically insulating material that delimits an empty cavity, and forms a plug to close the cavity. The sides of the trench are configured with a neck that determines the depth of the plug, and a first portion that tapers outwards from the neck as the distance from the bottom increases. Deep isolation trenches may be applied, in particular, to bipole and BiCMOS circuits.
摘要翻译：在半导体衬底中形成具有侧面和底部的深度隔离沟槽。侧面和底部都涂有电绝缘材料，其限定空腔，并形成一个塞子来封闭空腔。沟槽的侧面配置有确定插头的深度的颈部，以及随着距离底部的距离增加而从颈部向外逐渐变细的第一部分。特别是可以应用深度隔离沟槽到双极和BiCMOS电路。

33. 发明授权

US06180520B2 Multiple layer interconnects with low stray lateral capacitance 失效
标题翻译：具有低杂散横向电容的多层互连
公开(公告)号：US06180520B2
公开(公告)日：2001-01-30
申请号：US08826921
申请日：1997-04-08
申请人： Michel Marty , G{acute over (e)}rard Passemard , Graeme Wyborn
发明人： Michel Marty , G{acute over (e)}rard Passemard , Graeme Wyborn
IPC分类号： H01L2144
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to an interconnect structure wherein the upper surface of the first interconnect level is a tungsten layer, portions of the first interconnect level are insulated from one another by an insulator of the SOG type, portions of a second interconnect level are connected to portions of the first interconnect level by conductive pads formed in openings of an insulating layer, at least the lower part of which is of the SOG type, the walls and the bottom of the openings are covered with a thin titanium layer, and the openings are filled with a conductive material selected in the group including Al, Cu and aluminum alloys such as silicon, copper, and titanium alloys.
摘要翻译：本发明涉及互连结构，其中第一互连层的上表面是钨层，第一互连层的部分通过SOG类型的绝缘体彼此绝缘，第二互连层的部分连接到第一互连级的部分由形成在绝缘层的开口中的至少其下部分是SOG型的开口中的导电焊盘，开口的壁和底部覆盖有薄的钛层，并且开口是填充有选自Al，Cu和铝合金如硅，铜和钛合金的导电材料。

34. 发明授权

US6031445A Transformer for integrated circuits 有权
标题翻译：集成电路用变压器
公开(公告)号：US6031445A
公开(公告)日：2000-02-29
申请号：US199837
申请日：1998-11-25
申请人： Michel Marty , Herve Jaouen
发明人： Michel Marty , Herve Jaouen
IPC分类号： H01F27/28 , H01F41/04 , H01L21/02 , H01F5/00
CPC分类号： H01L28/10 , H01F27/2804 , H01F41/041 , H01F2017/0086 , Y10T29/4902
摘要： A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting lines, to form a first winding. Second conductive vias traverse the first, second and third insulating layers to connect said first and fourth pluralities of conducting lines to form a second winding, about and approximately concentric with said first winding.
摘要翻译：本发明提供了一种用于集成电路的变压器，包括四层导电线，它们由第一，第二和第三绝缘层相互隔开。第一导电通孔穿过第二绝缘层以连接所述第二和第三多条导线，以形成第一绕组。第二导电通孔横穿第一，第二和第三绝缘层，以连接所述第一和第四多条导线以形成与所述第一绕组大致同心的第二绕组。

35. 发明授权

US5976898A Localization of defects of a metallic layer of a semiconductor circuit 失效
标题翻译：半导体电路的金属层的缺陷的定位
公开(公告)号：US5976898A
公开(公告)日：1999-11-02
申请号：US770476
申请日：1996-12-20
申请人： Michel Marty , Alain Brun
发明人： Michel Marty , Alain Brun
IPC分类号： G01R31/311 , G01R31/26 , H01L21/00 , H01L21/66
CPC分类号： G01R31/311
摘要： A method for locating possible defects on an opaque layer deposited on a production wafer of a semiconductor circuit, consisting in locally radiating an upper surface of the wafer by means of a laser, and detecting the occurrence of a current in a diode constituted by a PN junction placed under the opaque layer to be examined.
摘要翻译：一种用于定位沉积在半导体电路的生产晶片上的不透明层上的可能的缺陷的方法，其包括通过激光局部地辐射晶片的上表面，并且检测由PN构成的二极管中的电流的出现连接处置于待检查的不透明层之下。

36. 发明申请

US20120261732A1 METHOD FOR FORMING A BACK-SIDE ILLUMINATED IMAGE SENSOR 有权
标题翻译：形成背面照明图像传感器的方法
公开(公告)号：US20120261732A1
公开(公告)日：2012-10-18
申请号：US13445013
申请日：2012-04-12
申请人： Michel Marty , François Roy , Jens Prima
发明人： Michel Marty , François Roy , Jens Prima
IPC分类号： H01L31/113 , H01L31/18
CPC分类号： H01L27/14689 , H01L27/1463 , H01L27/1464 , H01L27/14643 , H01L27/14687
摘要： A method for forming a back-side illuminated image sensor from a semiconductor substrate, including the steps of: a) thinning the substrate from its rear surface; b) depositing, on the rear surface of the thinned substrate, an amorphous silicon layer of same conductivity type as the substrate but of higher doping level; and c) annealing at a temperature enabling to recrystallized the amorphous silicon to stabilize it.
摘要翻译：一种用于从半导体衬底形成背面照明图像传感器的方法，包括以下步骤：a）从其后表面减薄衬底; b）在薄化衬底的后表面上沉积与衬底相同导电类型但具有较高掺杂水平的非晶硅层; 和c）在能够使非晶硅重结晶以使其稳定的温度下进行退火。

37. 发明申请

US20090256224A1 INTEGRATED CIRCUIT COMPRISING MIRRORS BURIED AT DIFFERENT DEPTHS 有权
标题翻译：包含不同深度的镜子的集成电路
公开(公告)号：US20090256224A1
公开(公告)日：2009-10-15
申请号：US12398872
申请日：2009-03-05
申请人： Perceval Coudrain , Philippe Coronel , Michel Marty , Matthieu Bopp
发明人： Perceval Coudrain , Philippe Coronel , Michel Marty , Matthieu Bopp
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14625 , H01L27/14645 , H01L27/14683 , H01L31/0232
摘要： A semiconductor structure including a first active area under which is buried a first reflective layer and a least one second active area under which is buried a second reflective layer, wherein the upper surface of the second reflective layer is closer to the upper surface of the structure than the upper surface of the first reflective layer.
摘要翻译：一种半导体结构，包括第一有源区，其下埋有第一反射层和至少一个第二有源区，在该第一有源区内掩埋有第二反射层，其中第二反射层的上表面更靠近该结构的上表面比第一反射层的上表面。

38. 发明授权

US07456071B2 Method for forming a strongly-conductive buried layer in a semiconductor substrate 有权
标题翻译：在半导体衬底中形成强导电掩埋层的方法
公开(公告)号：US07456071B2
公开(公告)日：2008-11-25
申请号：US11123318
申请日：2005-05-06
申请人： Michel Marty , Philippe Coronel , François Leverd
发明人： Michel Marty , Philippe Coronel , François Leverd
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/41708
摘要： An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.
摘要翻译：一种集成电路，其包括在基本上平行于主电路表面的平面的平面中确定的导电类型的掩埋层，其中该掩埋层的中间部分填充有金属型材料。

39. 发明申请

US20080272418A1 Semiconductor component comprising a buried mirror 审中-公开
公开(公告)号：US20080272418A1
公开(公告)日：2008-11-06
申请号：US12151085
申请日：2008-05-01
申请人： Sebastien Jouan , Michel Marty
发明人： Sebastien Jouan , Michel Marty
IPC分类号： H01L31/00 , H01L21/00
CPC分类号： H01L31/1804 , H01L31/02327 , H01L31/105 , H01L31/1085 , Y02E10/547 , Y02P70/521
摘要： A method for forming a buried mirror in a semiconductor component includes the steps of forming a structure comprising a semiconductor layer laid on an insulating layer covering a substrate; forming one or several openings in the semiconductor layer emerging at the surface of the insulating layer; eliminating a portion of the insulating layer, whereby a recess is formed; forming a second thin insulating layer against the wall of the recess; and forming a metal layer in the recess against the second insulating layer.

40. 发明授权

US06423996B1 Process for fabricating a metal-metal capacitor within an integrated circuit, and corresponding integrated circuit 有权
标题翻译：在集成电路内制造金属 - 金属电容器的工艺及相应的集成电路
公开(公告)号：US06423996B1
公开(公告)日：2002-07-23
申请号：US09658221
申请日：2000-09-08
申请人： Michel Marty , Herve Jaouen
发明人： Michel Marty , Herve Jaouen
IPC分类号： H01L27108
CPC分类号： H01L28/40
摘要： A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes and the dielectric layer. The integrated circuit comprises the insulating layer, a first metal layer which is on top of the lower insulating layer, and the upper insulating layer which is on top of the first metal layer. The capacitor comprises the first metal electrode, the second metal electrode, and the dielectric layer wherein each of the two metal electrodes is in contact with one side of the dielectric layer. The electrodes and the dielectric layer lie between the lower insulating layer, which supports a level of metallization (M1), and the upper insulating layer which covers this level of metallization.
摘要翻译：一种用于在集成电路内制造金属 - 金属电容器的工艺包括以下步骤：在下绝缘层的顶部上产生第一金属电极，第二金属电极和电介质层; 以及在所述两个金属电极和所述电介质层的顶部上沉积上绝缘层。集成电路包括绝缘层，位于下绝缘层顶部的第一金属层和位于第一金属层顶部的上绝缘层。电容器包括第一金属电极，第二金属电极和电介质层，其中两个金属电极中的每一个与电介质层的一侧接触。电极和电介质层位于支撑金属化水平（M1）的下绝缘层和覆盖这种金属化水平的上绝缘层之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式