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31. 发明授权

US5365475A Semiconductor memory device usable as static type memory and read-only memory and operating method therefor 失效
标题翻译：半导体存储器件可用作静态存储器和只读存储器及其操作方法
公开(公告)号：US5365475A
公开(公告)日：1994-11-15
申请号：US747204
申请日：1991-08-19
申请人： Tetsuya Matsumura , Shinichi Uramoto , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Shinichi Uramoto , Masahiko Yoshimoto
IPC分类号： G11C11/41 , G11C5/14 , G11C11/00 , G11C11/412 , G11C14/00
CPC分类号： G11C5/14 , G11C11/005 , G11C11/412
摘要： Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.
摘要翻译：半导体存储器件的每个存储单元包括连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，以及连接在节点和节点之间的晶体管。当制造节点时，每个节点在节目单元中连接到第一电位线和第二电源线中的任一个，并且当节点单元中的每个节点连接到节目单元中的任一个时被制造。电源电位被提供给第一电源线，并且电源电位或接地电位被选择性地提供给第二电源线。接地电位被提供给第一接地线，并且接地电位或供电电势被选择性地提供给第二接地线。

32. 发明授权

US5289406A Read only memory for storing multi-data 失效
标题翻译：只读存储器用于存储多数据
公开(公告)号：US5289406A
公开(公告)日：1994-02-22
申请号：US744098
申请日：1991-08-13
申请人： Shinichi Uramoto , Tetsuya Matsumura , Masahiko Yoshimoto , Kazuya Ishihara , Hiroshi Segawa
发明人： Shinichi Uramoto , Tetsuya Matsumura , Masahiko Yoshimoto , Kazuya Ishihara , Hiroshi Segawa
IPC分类号： G11C11/56 , G11C17/00
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译：只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。通过切换参考电位传输线的电位来改变存储单元中的存储数据。这使得能够将不同的数据位存储在一个存储单元中。

33. 发明授权

US5040143A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5040143A
公开(公告)日：1991-08-13
申请号：US526138
申请日：1990-05-22
申请人： Tetsuya Matsumura , Masahiko Yoshimoto
发明人： Tetsuya Matsumura , Masahiko Yoshimoto
IPC分类号： G11C5/14 , G11C7/20 , G11C11/00 , G11C11/412
CPC分类号： G11C11/412 , G11C11/005 , G11C5/14 , G11C7/20
摘要： First and second supply lines are connected to some or all of a plurality of memory cells included in a memory cell array. Only the first supply line is connected to the remaining memory cells. When a voltage of H level is supplied to the first and second supply lines, all memory cells function as SRAM memory cells in which stored information can be rewritten. Meanwhile when H level is applied to the first supply line and L level is applied to the second supply lines, memory cells to which both the first and second supply lines are connected are set to a state in which information of the logic "1" or "0" is fixedly stored. Namely, they function as ROM memory cells. At this time, the remaining member cells to which only the first supply line is connected function as SRAM memory cells. In this manner, by switching the voltages applied to the second supply line, some or all of the memory cell arrays function as SRAM or ROM.
摘要翻译：第一和第二供电线连接到包括在存储单元阵列中的多个存储单元中的一些或全部。只有第一条电源线连接到剩余的存储单元。当H电平被提供给第一和第二供电线时，所有存储单元都用作可以重写存储信息的SRAM存储单元。同时，当H电平施加到第一电源线并且L电平施加到第二电源线时，将第一和第二电源线连接的存储单元设置为逻辑“1”或 “0”被固定地存储。即，它们用作ROM存储单元。此时，仅连接第一电源线的剩余成员单元作为SRAM存储单元。以这种方式，通过切换施加到第二电源线的电压，一些或全部存储单元阵列用作SRAM或ROM。

34. 发明授权

US4953128A Variable delay circuit for delaying input data 失效
标题翻译：用于延迟输入数据的可变延迟电路
公开(公告)号：US4953128A
公开(公告)日：1990-08-28
申请号：US133790
申请日：1987-12-16
申请人： Hiroyuki Kawai , Masahiko Yoshimoto
发明人： Hiroyuki Kawai , Masahiko Yoshimoto
IPC分类号： G11C7/00 , G11C7/10 , G11C8/04 , G11C19/00 , H04N7/62
CPC分类号： H04N21/4302 , G11C7/1006 , G11C8/04 , H04N21/242
摘要： An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay. Therefore, a delayed input data can be obtained as an output data.
摘要翻译：地址计数器（2）对时钟脉冲进行顺序计数，以向计数器（3）和解码器（4）提供作为地址信号的计数值。比较从延迟数据产生电路（8）施加的延迟数据与地址信号，并将复位信号与地址计数器（2）相互重合的同时检测电路（3）进行比较。地址计数器（2）在将地址计数复位到预定值之后，响应于复位信号顺序重复上述操作。解码器（4）指定包含在存储器件中的存储器单元，用于响应于地址信号执行读和写操作。数据输出电路（6）和数据输入电路（5）响应于从控制电路（7）输出的控制信号，顺序地向指定的存储单元执行读和写操作。结果，预先写入的输入数据被延迟地读出并输出。因此，可以获得延迟的输入数据作为输出数据。

35. 再颁专利

USRE32993E Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：USRE32993E
公开(公告)日：1989-07-18
申请号：US97770
申请日：1987-09-17
申请人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
发明人： Kenji Anami , Masahiko Yoshimoto , Hirofumi Shinohara , Osamu Tomisawa
IPC分类号： G11C11/417 , G11C5/02 , G11C5/06 , G11C8/12 , G11C8/14 , G11C11/41
CPC分类号： G11C5/06 , G11C5/02 , G11C8/12 , G11C8/14
摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines flow resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.

36. 发明授权

US4521704A Differential amplifying circuit 失效
标题翻译：差分放大电路
公开(公告)号：US4521704A
公开(公告)日：1985-06-04
申请号：US462204
申请日：1983-01-31
申请人： Hirofumi Shinohara , Osamu Tomisawa , Kenji Anami , Masahiko Yoshimoto
发明人： Hirofumi Shinohara , Osamu Tomisawa , Kenji Anami , Masahiko Yoshimoto
IPC分类号： G11C11/417 , H03F3/26 , H03F3/45 , H03K5/02
CPC分类号： H03F3/265 , H03F3/45076 , H03F2203/45318 , H03F2203/45394
摘要： A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.
摘要翻译：差分放大电路包括一对主放大电路（5a，5b），每一个具有至少三个输入端和至少一个输出端，以及一对辅助放大电路（6a，6b），每一个具有至少一个输入端。免费输入（D1，＆amp; upbar＆D）连接到所述一对辅助放大电路（6a，6b）的输入端，主放大电路（5a，5b）的输出（D2，＆amp; upbar＆D）输入到所述一对主放大电路（5a，5b）中的至少一对输入端，所述互补输入（D2，＆amp;上和下）也连接到另一个至少一对输入端，并且所述输出辅助放大电路（6a，6b）进一步连接到另外的至少一对输入端。

37. 发明授权

US08787075B2 Low-voltage semiconductor memory 有权
标题翻译：低压半导体存储器
公开(公告)号：US08787075B2
公开(公告)日：2014-07-22
申请号：US13816718
申请日：2011-08-14
申请人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Yohei Nakata , Shunsuke Okumura
发明人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Yohei Nakata , Shunsuke Okumura
IPC分类号： G11C11/00 , G11C11/412 , G11C11/417 , G11C8/12 , G11C15/04 , G11C11/413 , G11C8/14 , G11C15/00
CPC分类号： G11C11/417 , G11C8/12 , G11C8/14 , G11C11/412 , G11C11/413 , G11C15/00 , G11C15/04 , G11C29/74 , G11C2211/5641
摘要： Provided is memory which is capable of dynamically changing memory cell bit reliability and of switching the operating mode so as to accommodate process variations, thereby reducing the operating voltage. The memory is provided with a mode control line selection circuit for dividing mode control lines in to word units and using control line selection signals and global control signals to control the mode control lines divided into word units, and a word line selection circuit for dividing the word lines that control the conduction of switching unit into word units and using word line selection signals and global word signals to control the word lines divided into word units. The mode control line switching circuit is used to switch between a 1 bit/1 cell mode and a 1 bit/n cell mode in word units.
摘要翻译：提供了能够动态地改变存储单元位可靠性和切换操作模式以适应过程变化的存储器，从而降低工作电压。存储器设置有模式控制线选择电路，用于将模式控制线分成单位，并且使用控制线选择信号和全局控制信号来控制分成字单元的模式控制线，以及字线选择电路，用于将控制开关单元导通到单元的字线，并使用字线选择信号和全局字信号来控制划分为字单位的字线。模式控制线切换电路用于以单位单位在1位/ 1个单元模式和1位/ n单元模式之间切换。

38. 发明申请

US20130029684A1 SENSOR NETWORK SYSTEM FOR ACUIRING HIGH QUALITY SPEECH SIGNALS AND COMMUNICATION METHOD THEREFOR 失效
标题翻译：用于获取高质量语音信号的传感器网络系统及其通信方法
公开(公告)号：US20130029684A1
公开(公告)日：2013-01-31
申请号：US13547426
申请日：2012-07-12
申请人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Shintaro Izumi
发明人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Shintaro Izumi
IPC分类号： H04W24/00
CPC分类号： H04R3/005 , G10L2021/02166 , H04R1/406 , H04R2201/401
摘要： A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
摘要翻译：包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置，将位于最靠近信号源的节点装置指定为簇头节点装置，并发送信息源信号源和指定的簇头节点设备的位置到每个节点设备，将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。每个节点设备对来自信号源的接收信号执行强调处理，并将强调信号发送到基站。

39. 发明申请

US20120286987A1 AD CONVERTER AND TD CONVERTER CONFIGURED WITHOUT OPERATIONAL AMPLIFIER AND CAPACITOR 失效
标题翻译： AD转换器和TD转换器配置无运算放大器和电容器
公开(公告)号：US20120286987A1
公开(公告)日：2012-11-15
申请号：US13470605
申请日：2012-05-14
申请人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
发明人： Hiroshi KAWAGUCHI , Masahiko Yoshimoto , Toshihiro Konishi , Shintaro Izumi
IPC分类号： H03M1/50
CPC分类号： H03M1/50 , H03M3/416
摘要： An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
摘要翻译： AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分，将模拟输入电压转换为相应的延迟时间，并输出时域数据。 N级的环形振荡器电路部分输入时域数据，误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息，并将延迟信息传播到环振荡电路是后续阶段的一部分。计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数，并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。

40. 发明授权

US08238140B2 Semiconductor memory and program 有权
标题翻译：半导体存储器和程序
公开(公告)号：US08238140B2
公开(公告)日：2012-08-07
申请号：US12809684
申请日：2009-01-07
申请人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Shunsuke Okumura , Hidehiro Fujiwara
发明人： Masahiko Yoshimoto , Hiroshi Kawaguchi , Shunsuke Okumura , Hidehiro Fujiwara
IPC分类号： G11C11/24 , G11C11/00 , G11C7/00 , G11C7/02 , G11C29/00
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory wherein the bit reliability of the memory cells can be dynamically varied depending on the application or the memory status, the operation stability is ensured, and thereby a low power consumption and a high reliability are realized. Either a mode (a 1-bit/1-cell mode) in which one bit is composed of one memory cell or a mode (a 1-bit/n-cell mode) in which one bit is composed of n (n is two or more) connected memory cells is dynamically selected. When the 1-bit/n-cell mode is selected, the read/write stability of one bit is enhanced, the cell current during read is increased (read is speeded up), and a bit error, if occurs, is self-corrected. Especially, a pair of CMOS transistors and a control line for performing control so as to permit the CMOS transistors to conduct are added between the data holding nodes of n adjacent memory cells. With this, the word line (WL) is controlled, and thereby the operation stability is further improved.
摘要翻译：可以根据应用或存储器状态来动态地改变存储器单元的位可靠性的存储器，从而确保操作稳定性，从而实现低功耗和高可靠性。一个位由一个存储器单元组成的模式（1位/ 1单元模式）或其中一个位由n组成的模式（1位/ n单元模式）或更多）连接的存储器单元被动态地选择。当选择1位/ n单元模式时，增加了一位的读/写稳定性，读取期间的单元电流增加（读取速度加快），如果出现位错误，则自校正。特别地，在n个相邻的存储单元的数据保持节点之间添加一对CMOS晶体管和用于执行控制以允许CMOS晶体管导通的控制线。由此，对字线（WL）进行控制，从而进一步提高操作稳定性。

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