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    • 1. 发明申请
    • SENSOR NETWORK SYSTEM FOR ACUIRING HIGH QUALITY SPEECH SIGNALS AND COMMUNICATION METHOD THEREFOR
    • 用于获取高质量语音信号的传感器网络系统及其通信方法
    • US20130029684A1
    • 2013-01-31
    • US13547426
    • 2012-07-12
    • Hiroshi KAWAGUCHIMasahiko YoshimotoShintaro Izumi
    • Hiroshi KAWAGUCHIMasahiko YoshimotoShintaro Izumi
    • H04W24/00
    • H04R3/005G10L2021/02166H04R1/406H04R2201/401
    • A sensor network system including node devices connected in a network via predetermined propagation paths collects data measured at each node device to be aggregated into one base station via a time-synchronized sensor network system. The base station calculates a position of the signal source based on the angle estimation value of the signal from each node device and position information thereof, designates a node device located nearest to the signal source as a cluster head node device, and transmits information of the position of the signal source and the designated cluster head node device to each node device, to cluster each node device located within the number of hops from the cluster head node device as a node device belonging to each cluster. Each node device performs an emphasizing process on the received signal from the signal source, and transmits an emphasized signal to the base station.
    • 包括经由预定传播路径连接在网络中的节点设备的传感器网络系统经由时间同步的传感器网络系统收集在每个节点设备测量的要聚合成一个基站的数据。 基站基于来自各节点装置的信号的角度估计值及其位置信息来计算信号源的位置,将位于最靠近信号源的节点装置指定为簇头节点装置,并发送信息源 信号源和指定的簇头节点设备的位置到每个节点设备,将位于簇头节点设备内的跳数内的每个节点设备聚类为属于每个集群的节点设备。 每个节点设备对来自信号源的接收信号执行强调处理,并将强调信号发送到基站。
    • 2. 发明申请
    • AD CONVERTER AND TD CONVERTER CONFIGURED WITHOUT OPERATIONAL AMPLIFIER AND CAPACITOR
    • AD转换器和TD转换器配置无运算放大器和电容器
    • US20120286987A1
    • 2012-11-15
    • US13470605
    • 2012-05-14
    • Hiroshi KAWAGUCHIMasahiko YoshimotoToshihiro KonishiShintaro Izumi
    • Hiroshi KAWAGUCHIMasahiko YoshimotoToshihiro KonishiShintaro Izumi
    • H03M1/50
    • H03M1/50H03M3/416
    • An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
    • AD转换器包括输入模拟输入电压和采样时钟的VT转换器电路部分,将模拟输入电压转换为相应的延迟时间,并输出时域数据。 N级的环形振荡器电路部分输入时域数据,误差传播电路部分从前级的环形振荡电路部分的相位信息中取出包含量化误差的延迟信息,并将延迟信息传播到环 振荡电路是后续阶段的一部分。 计数器电路部分测量每个级的环形振荡器电路部分的输出振荡波形的波数,并且输出信号发生器部分根据每个计数器电路部分的输出计数值产生输出信号。 复位部分将采样时钟复位每个误差传播电路部分和每个计数器电路部分。
    • 3. 发明申请
    • Semiconductor Memory Device for Reducing Charge/Discharge Power of Write Bitlines
    • 用于降低写入位线的充电/放电功率的半导体存储器件
    • US20120314486A1
    • 2012-12-13
    • US13492231
    • 2012-06-08
    • Masahiko YOSHIMOTOHiroshi KAWAGUCHIShunsuke YOSHIMOTO
    • Masahiko YOSHIMOTOHiroshi KAWAGUCHIShunsuke YOSHIMOTO
    • G11C11/00
    • G11C11/419
    • It is aimed to provide a semiconductor memory device capable of solving a half-select problem in 8Tr SRAMs and, simultaneously, achieving a reduction in charge/discharge power in a half-selected column, which has been a problem with the conventional write-back scheme. An 8Tr SRAM includes 1) a bitline half driver circuit which is capable of reading retention data from read bitline (RBL) of each memory cell of a memory cell group in a column direction and drives the write bitlines only for the memory cells of a half-selected column according to the read data, 2) a selection signal circuit to which an enable signal and a column selection signal of the bitline half driver circuit are input and which activates the bitline half driver circuit, and 3) an equalizer circuit which equalizes the write bitlines of the memory cell group in the column direction and does not precharge the write bitlines.
    • 旨在提供一种能够解决8Tr SRAM中的半选择问题的半导体存储器件,并且同时实现半选择列中的充电/放电功率的降低,这已经是常规回写的问题 方案。 8Tr SRAM包括1)位线半驱动器电路,其能够从列方向读取存储器单元组的每个存储单元的读位线(RBL)读取保留数据,并仅驱动一半的存储单元的写位线 - 根据读取的数据选择的列; 2)选择信号电路,其中输入有位线半驱动电路的使能信号和列选择信号,并且激活位线半驱动电路;以及3)均衡器电路 在列方向上写存储单元组的位线,并且不预写写位线。
    • 5. 发明申请
    • STRAND GUIDING APPARATUS FOR CONTINUOUS CASTING EQUIPMENT
    • 连续铸造设备的指导装置
    • US20110155342A1
    • 2011-06-30
    • US12978880
    • 2010-12-27
    • Hiroshi KAWAGUCHIFumiki AsanoKazunori Okada
    • Hiroshi KAWAGUCHIFumiki AsanoKazunori Okada
    • B22D11/16
    • B22D11/1281
    • A strand guiding apparatus includes a plurality of pairs of rollers arranged along a moving direction of a strand, a plurality of drive motors for generating driving forces to drive the pairs of rollers, a plurality of worm reducers for transmitting the driving forces of the drive motors to the pairs of rollers while reducing the rotational speed of the drive motors, each worm reducer having a worm extending in a direction orthogonal to an axis of the corresponding roller, and operable to transmit a load occurring at the roller to the corresponding drive motor, and a control unit for controlling the respective rotational speeds of the rollers and/or the respective driving forces of the drive motors based on the load to the drive motors. The reliable control for drive rollers can be attained to have a proper rotational speed without causing a reduction in surface quality and chatter in a strand guiding apparatus for continuous casting equipment using worm reducers.
    • 线引导装置包括沿着绞合线的移动方向布置的多对滚子,用于产生驱动力以驱动该对滚子的多个驱动马达,用于传递驱动马达的驱动力的多个蜗杆减速器 在减少驱动马达的旋转速度的同时,每个蜗轮减速器具有在与相应的滚子的轴线正交的方向上延伸的蜗杆,并且可操作地将在滚子处发生的载荷传递到相应的驱动马达, 以及控制单元,用于基于对驱动马达的负载来控制各个滚子的转速和/或驱动马达的相应驱动力。 可以实现驱动辊的可靠控制,以具有适当的转速,而不会导致使用蜗杆减速器的连续铸造设备的钢绞线引导装置中的表面质量下降和颤动。
    • 6. 发明申请
    • INSPECTION SYSTEM AND INSPECTION METHOD
    • 检查系统和检查方法
    • US20100158348A1
    • 2010-06-24
    • US12719390
    • 2010-03-08
    • Hiroshi KAWAGUCHI
    • Hiroshi KAWAGUCHI
    • G06K9/00
    • G06T5/40G01N21/956G01R31/309G06T5/009G06T2207/10152G06T2207/30148
    • The inspection system arbitrarily selects from among a plurality of optical conditions to change a distribution of reflected or diffracted light component from an object being inspected. The inspection system has a one- or two-dimensional optoelectric conversion image sensor, optically acquires an image of the object by scanning a stage on which the object is mounted or scanning the image sensor, and processes the image to check for defects in the object. Under each optical condition (illumination optical system, detection optical system, scan direction, etc.) the object being inspected is imaged and, based on the brightness distribution and contrast in the detection field of the image sensor, image sensor output correction data is generated to correct the output of the image sensor.
    • 检查系统从多个光学条件中任意选择以改变被检测物体的反射或衍射光分量的分布。 检查系统具有一维或二维光电转换图像传感器,通过扫描安装对象的台面或扫描图像传感器来光学地获取对象的图像,并处理图像以检查对象中的缺陷 。 在每个光学条件(照明光学系统,检测光学系统,扫描方向等)下,对被检查对象进行成像,并且基于图像传感器的检测区域中的亮度分布和对比度,生成图像传感器输出校正数据 以校正图像传感器的输出。