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31. 发明授权

US08536706B2 Method for fabricating semiconductor device and semiconductor device 有权
公开(公告)号：US08536706B2
公开(公告)日：2013-09-17
申请号：US13707359
申请日：2012-12-06
申请人： Yumi Hayashi , Atsuko Sakata , Kei Watanabe , Noriaki Matsunaga , Shinichi Nakao , Makoto Wada , Hiroshi Toyoda
发明人： Yumi Hayashi , Atsuko Sakata , Kei Watanabe , Noriaki Matsunaga , Shinichi Nakao , Makoto Wada , Hiroshi Toyoda
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L21/76814 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

32. 发明申请

US20130134592A1 WIRE AND SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20130134592A1
公开(公告)日：2013-05-30
申请号：US13684297
申请日：2012-11-23
申请人： Yuichi YAMAZAKI , Makoto Wada , Masayuki Kitamura , Tadashi Sakai
发明人： Yuichi YAMAZAKI , Makoto Wada , Masayuki Kitamura , Tadashi Sakai
IPC分类号： H05K1/09 , H01L23/532
CPC分类号： H01L23/53276 , B82Y10/00 , B82Y30/00 , B82Y99/00 , H01L2924/0002 , H05K1/097 , Y10S977/734 , Y10S977/762 , H01L2924/00
摘要： A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.

33. 发明申请

US20130075929A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130075929A1
公开(公告)日：2013-03-28
申请号：US13541954
申请日：2012-07-05
申请人： Masayuki Katagiri , Yuichi Yamazaki , Makoto Wada , Tadashi Sakai , Naoshi Sakuma , Mariko Suzuki
发明人： Masayuki Katagiri , Yuichi Yamazaki , Makoto Wada , Tadashi Sakai , Naoshi Sakuma , Mariko Suzuki
IPC分类号： H01L21/768 , H01L23/522 , B82Y99/00 , B82Y40/00
CPC分类号： H01L23/5226 , B82Y40/00 , H01L21/76876 , H01L21/76879 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of an embodiment includes: a substrate; a first catalytic metal film on the substrate; graphene on the first catalytic metal film; an interlayer insulating film on the graphene; a contact hole penetrating through the interlayer insulating film; a conductive film at the bottom portion of the contact hole, the conductive film being electrically connected to the graphene; a second catalytic metal film on the conductive film, the second catalytic metal film being subjected to plasma processing with at least one kind of gas selected from hydrogen, nitrogen, ammonia, and rare gas; and carbon nanotubes on the second catalytic metal film.
摘要翻译：实施例的半导体器件包括：衬底; 在基板上的第一催化金属膜; 第一催化金属膜上的石墨烯; 石墨烯上的层间绝缘膜; 穿过层间绝缘膜的接触孔; 所述导电膜在所述接触孔的底部，所述导电膜与所述石墨烯电连接; 在所述导电膜上的第二催化金属膜，所述第二催化金属膜用选自氢，氮，氨和稀有气体中的至少一种气体进行等离子体处理; 和第二催化金属膜上的碳纳米管。

34. 发明授权

US08344509B2 Method for fabricating semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US08344509B2
公开(公告)日：2013-01-01
申请号：US12652204
申请日：2010-01-05
申请人： Yumi Hayashi , Atsuko Sakata , Kei Watanabe , Noriaki Matsunaga , Shinichi Nakao , Makoto Wada , Hiroshi Toyoda
发明人： Yumi Hayashi , Atsuko Sakata , Kei Watanabe , Noriaki Matsunaga , Shinichi Nakao , Makoto Wada , Hiroshi Toyoda
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/76814 , H01L21/76843 , H01L21/76849 , H01L21/76856 , H01L21/76867 , H01L21/76877 , H01L21/76883 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

35. 发明授权

US08058730B2 Semiconductor device having a multilayered interconnection structure 有权
标题翻译：具有多层互连结构的半导体器件
公开(公告)号：US08058730B2
公开(公告)日：2011-11-15
申请号：US12239236
申请日：2008-09-26
申请人： Makoto Wada , Kazuyuki Higashi
发明人： Makoto Wada , Kazuyuki Higashi
IPC分类号： H01L29/06
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与第一导电构件的上表面的一部分接触的第二导电构件，形成在第一绝缘膜上以与第一导电构件的上表面的一部分接触的第二绝缘膜，以及包括除Si之外的第一绝缘膜中包含的元素中的至少一种元素; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

36. 发明授权

US07875976B2 Semiconductor device including a silicide layer and a dielectric layer 有权
标题翻译：包括硅化物层和电介质层的半导体器件
公开(公告)号：US07875976B2
公开(公告)日：2011-01-25
申请号：US11868011
申请日：2007-10-05
申请人： Makoto Wada , Takamasa Usui , Kazuya Ohuchi
发明人： Makoto Wada , Takamasa Usui , Kazuya Ohuchi
IPC分类号： H01L23/52
CPC分类号： H01L23/485 , H01L21/76831 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
摘要翻译：在本发明的一个方面中，半导体器件可以包括半导体衬底，设置在半导体衬底上的硅化物层，设置在半导体衬底上的电介质层，设置在硅化物层上的接触层，设置在该半导体衬底上的金属层电介质层，经由接触层与硅化物层电连接，设置在介电层和金属层之间的扩散阻挡层，其中接触层包括设置在金属层中的第一金属元件，设置在金属层中的第二金属元件扩散阻挡层和设置在硅化物层和Si元件中的第三金属中的至少一个。

37. 发明申请

US20090206491A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090206491A1
公开(公告)日：2009-08-20
申请号：US12361979
申请日：2009-01-29
申请人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
发明人： Makoto Wada , Akihiro Kajita , Kazuyuki Higashi
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a connecting member formed above the semiconductor substrate configured to electrically connect upper and lower conductive members; a first insulating film formed in the same layer as the connecting member; a wiring formed on the connecting member, the wiring including a first region and a second region, the first region contacting with a portion of an upper surface of the connecting member, and the second region located on the first region and having a width greater than that of the first region; and a second insulating film formed on the first insulating film so as to contact with at least a portion of the first region of the wiring and with a bottom surface of the second region.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底之上的连接构件，构造成电连接上导电构件和下导电构件; 形成在与所述连接构件相同的层中的第一绝缘膜; 形成在所述连接构件上的布线，所述布线包括第一区域和第二区域，所述第一区域与所述连接构件的上表面的一部分接触，所述第二区域位于所述第一区域上，并且宽度大于第一区域; 以及形成在所述第一绝缘膜上以与所述布线的所述第一区域的至少一部分和所述第二区域的底表面接触的第二绝缘膜。

38. 发明授权

US07304384B2 Semiconductor device with a barrier film which contains manganese 有权
标题翻译：具有含锰的阻挡膜的半导体器件
公开(公告)号：US07304384B2
公开(公告)日：2007-12-04
申请号：US11063876
申请日：2005-02-24
申请人： Junichi Koike , Makoto Wada , Shingo Takahashi , Noriyoshi Shimizu , Hideki Shibata , Satoshi Nishikawa , Takamasa Usui , Hayato Nasu , Masaki Yoshimaru
发明人： Junichi Koike , Makoto Wada , Shingo Takahashi , Noriyoshi Shimizu , Hideki Shibata , Satoshi Nishikawa , Takamasa Usui , Hayato Nasu , Masaki Yoshimaru
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76844 , H01L21/76831 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an interlevel insulating film disposed on a semiconductor substrate and having an opening formed therein. An interconnection main layer, which contains Cu as a main component, is embedded in the opening. A barrier film is interposed between the interlevel insulating film and the interconnection main layer within the opening. The barrier film contains, as a main component, a compound of a predetermined metal element with a component element of the interlevel insulating film.
摘要翻译：半导体器件包括设置在半导体衬底上并具有形成在其中的开口的层间绝缘膜。将包含Cu作为主要成分的互连主层嵌入开口部。隔离膜介于开口内的层间绝缘膜和互连主层之间。作为主要成分，阻挡膜含有具有层间绝缘膜的成分元素的预定金属元素的化合物。

39. 发明授权

US07109623B2 Motor and electrically-driven fan employing the same 有权
标题翻译：电机和电动风扇采用相同的
公开(公告)号：US07109623B2
公开(公告)日：2006-09-19
申请号：US11048733
申请日：2005-02-03
申请人： Makoto Wada , Akitomo Yamashita
发明人： Makoto Wada , Akitomo Yamashita
IPC分类号： H02K21/22 , H02K5/16 , H02K7/14
CPC分类号： F04D29/051 , F04D25/062 , F04D25/064 , F16C39/063 , F16C2360/46 , H02K1/2786 , H02K7/085 , H02K7/14 , H02K29/08
摘要： An electrically-driven fan 1 comprises a base portion 2; a bearing portion 11; a stator 13 including iron core portions 15 and coils 16; a rotor 4 including a rotary shaft 20 and a cylindrical magnet 22; blowing blades 5; and a rotor position detector 23 which is disposed on a side of the cylindrical magnet 22 near to the base portion 2, with a gap of predetermined width relative to the cylindrical magnet 22; wherein the cylindrical magnet 22 includes a thin-walled portion 24 in which an effective thickness of one end part thereof near to the rotor position detector 23 is made smaller than an effective thickness of the other end part thereof.
摘要翻译：电动风扇1包括基部2; 轴承部11; 包括铁芯部分15和线圈16的定子13; 包括旋转轴20和圆柱形磁体22的转子4; 吹风叶片5; 以及转子位置检测器23，其设置在圆筒形磁体22的靠近基部2的一侧，相对于圆柱形磁体22具有预定宽度的间隙; 其中，圆柱形磁体22包括薄壁部分24，其中其一个端部靠近转子位置检测器23的有效厚度小于其另一端部的有效厚度。

40. 发明授权

US08759162B2 Nonvolatile semiconductor memory device and method of manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08759162B2
公开(公告)日：2014-06-24
申请号：US13172330
申请日：2011-06-29
申请人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
发明人： Makoto Wada , Kazuyuki Higashi , Naofumi Nakamura , Tsuneo Uenaka
IPC分类号： H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

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