专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07480198B2 Semiconductor memory device and driving method of semiconductor memory device 失效
标题翻译：半导体存储器件及半导体存储器件的驱动方法
公开(公告)号：US07480198B2
公开(公告)日：2009-01-20
申请号：US11680999
申请日：2007-03-01
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/12 , G11C7/18 , G11C11/404 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002 , G11C2207/005 , G11C2207/2281 , G11C2211/4016
摘要： This disclosure concerns a semiconductor memory device comprising memory cells; word lines connected to gates of the memory cells; bit lines connected to drains or sources of the memory cells and transmitting data of the memory cells; sense nodes connected to the bit lines and transmitting data of the memory cells; transfer gates connected to between the bit lines and the sense nodes; and latch circuits latching data to the sense nodes, wherein in a data read operation, a selection word line is in an inactive state during a latch period which is from immediately before the latch circuits start a data latch operation until when the transfer gate disconnects the bit lines from the sense nodes after the latch operation, the selection word line being one of the word lines and being connected to selection memory cells from which data is to be read to the sense nodes.
摘要翻译：本公开涉及包括存储器单元的半导体存储器件; 连接到存储器单元的门的字线; 连接到存储器单元的漏极或源极的位线，并传送存储器单元的数据; 连接到位线的感测节点和发送存储器单元的数据; 连接到位线和感测节点之间的传输门; 并且锁存电路将数据锁存到感测节点，其中在数据读取操作中，在从锁存电路开始数据锁存操作之前的锁存时段期间，选择字线处于非活动状态，直到传输门断开在锁存操作之后，来自感测节点的位线，选择字线是字线之一，并且连接到选择存储器单元，数据将从其读取到感测节点。

32. 发明申请

US20060044794A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060044794A1
公开(公告)日：2006-03-02
申请号：US11056243
申请日：2005-02-14
申请人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
发明人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
IPC分类号： F21S2/00
CPC分类号： G11C7/14 , G11C11/404 , G11C11/4091 , G11C11/4099 , G11C2211/4016
摘要： A semiconductor memory device comprises memory cells that store data by accumulating or discharging an electric charge; memory cell arrays that have a plurality of the memory cells disposed in a matrix; a plurality of word lines that are connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines that are connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells that are arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers that detect data within the memory cells by using an average value of electric characteristics of the dummy cells that plurality of switching elements that electrically connect four or more of the bit lines in order to generate the reference signal.
摘要翻译：半导体存储器件包括通过累积或放电来存储数据的存储器单元; 具有设置在矩阵中的多个存储单元的存储单元阵列; 连接到排列在存储单元阵列中的存储单元的多个字线; 连接到排列在存储单元阵列的列中的存储单元的多个位线; 多个虚拟单元，其被布置在存储单元阵列的行方向上并连接到位线; 读出放大器，通过使用电连接四个或更多个位线的多个开关元件的虚拟单元的电特性的平均值来检测存储单元内的数据，以便产生参考信号。

33. 发明授权

US06842362B2 Magnetic random access memory 失效
标题翻译：磁性随机存取存储器
公开(公告)号：US06842362B2
公开(公告)日：2005-01-11
申请号：US10368609
申请日：2003-02-20
申请人： Katsuyuki Fujita , Yoshihisa Iwata
发明人： Katsuyuki Fujita , Yoshihisa Iwata
IPC分类号： G11C11/15 , G11C8/08 , G11C11/16 , G11C11/00
CPC分类号： G11C8/08 , G11C11/16
摘要： One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, a differential amplifier, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. At this moment, a value of the write current is restricted to a value which does not exceed VLIMIT/R1 by the differential amplifier. R1 is a wiring resistance of the write word line.
摘要翻译：写字线的一端连接到解码器/驱动器单元。解码器/驱动器单元由P沟道MOS晶体管，N沟道MOS晶体管，差分放大器和NAND电路构成。当写入，CHRDY和RA1都变为“H”时，来自NAND电路的输出信号变为“H”，并且写入电流流过写入字线。此时，写入电流的值被差分放大器限制为不超过VLIMIT / R1的值。 R1是写字线的布线电阻。

34. 发明授权

US06567330B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06567330B2
公开(公告)日：2003-05-20
申请号：US10102981
申请日：2002-03-22
申请人： Katsuyuki Fujita , Takashi Ohsawa
发明人： Katsuyuki Fujita , Takashi Ohsawa
IPC分类号： G11C702
CPC分类号： G11C7/06
摘要： A semiconductor memory device has a memory cell array including memory cells; a reference current generating circuit which generates a reference current; a reference voltage generating circuit which generates a reference voltage in a reference node on the basis of the reference current generated by the reference current generating circuit; a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data potential in a sense node on the basis of the output current and the reference current; and a second sense circuit which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.
摘要翻译：半导体存储器件具有包括存储单元的存储单元阵列; 产生参考电流的参考电流产生电路; 参考电压产生电路，其基于由参考电流产生电路产生的参考电流在参考节点中产生参考电压; 第一感测电路，其基于所选存储单元的单元电流产生输出电流，并且基于输出电流和参考电流在感测节点中产生数据电位; 以及第二感测电路，通过将感测节点中的数据电位与参考节点中的参考电压进行比较来检测保持在所选择的存储器单元中的数据。

35. 发明授权

US5873932A Method for improving light-fastness of reversible thermochromic compositions at the time of color development 失效
标题翻译：在显色时提高可逆热变色组合物的耐光性的方法
公开(公告)号：US5873932A
公开(公告)日：1999-02-23
申请号：US760209
申请日：1996-12-04
申请人： Katsuyuki Fujita , Yutaka Shibahashi , Yoshiaki Ono
发明人： Katsuyuki Fujita , Yutaka Shibahashi , Yoshiaki Ono
IPC分类号： G01K11/16 , B41M5/30 , B41M5/333 , B41M5/337 , C08K5/00 , C08K5/02 , C08K5/03 , C08K5/13 , C08L101/00 , C09K3/00 , C09K9/02 , C09K15/08 , C09D11/02
CPC分类号： C09K9/02 , B41M5/305 , B41M5/3335 , B41M5/3375
摘要： A method of causing metachromatism by the use of a reversible thermochromic composition comprising (a) an electron donating compound, (b) an electron accepting compound and (c) a metachromatic temperature adjuster, wherein;(d) an electron accepting, light-fastness providing agent represented by Formula I: ##STR1## wherein n represents an integer of 5 to 17 to form a straight-chain or branched alkyl group; X and Y each represent a straight-chain or branched alkyl group having 1 to 4 carbon atoms, or a halogen atom; and p and m each represent an integer of 0 to 3;is brought into presence in an amount of 0.3 part by weight to 70 parts by weight based on 1.0 part by weight of the component-(a) electron donating compound.The light-fastness of the reversible thermochromic composition at the time of color development can be greatly improved.
摘要翻译：一种通过使用可逆热变色组合物引起变质反应的方法，其包含（a）给电子化合物，（b）电子接受化合物和（c）异色温度调节剂，其中：（d）由式I表示的电子接受耐光性提供剂：其中n表示5〜17的整数，形成直链或支链烷基; X和Y各自表示具有1〜4个碳原子的直链或支链烷基或卤素原子; p和m各自表示0〜3的整数，以（a）给电子化合物1.0重量份计，以0.3重量份〜70重量份的量存在。显色时可逆热变色组合物的耐光性可大大提高。

36. 发明授权

US08498145B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08498145B2
公开(公告)日：2013-07-30
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包含选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

37. 发明授权

US08369129B2 Semiconductor memory device with variable resistance element 有权
标题翻译：具有可变电阻元件的半导体存储器件
公开(公告)号：US08369129B2
公开(公告)日：2013-02-05
申请号：US12818028
申请日：2010-06-17
申请人： Katsuyuki Fujita , Kenji Tsuchida
发明人： Katsuyuki Fujita , Kenji Tsuchida
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C2013/0054
摘要： According to one embodiment, a semiconductor memory device includes a variable resistance element configured to store data “0” and data “1” in accordance with a change in resistance value, a current generator configured to generate a reference current for determining data of the variable resistance element, and having an admittance middle between an admittance of a variable resistance element storing data “0” and an admittance of a variable resistance element storing data “1”, and a sense amplifier includes a first input terminal connected to the variable resistance element and a second input terminal connected to the current generator, and configured to compare currents of the first input terminal and the second input terminal.
摘要翻译：根据一个实施例，半导体存储器件包括可变电阻元件，其被配置为根据电阻值的变化来存储数据0和数据1;电流发生器，被配置为产生用于确定可变电阻元件的数据的参考电流;以及在存储数据0的可变电阻元件的导纳与存储数据1的可变电阻元件的导纳之间的导纳中心处的导纳和感测放大器包括连接到可变电阻元件的第一输入端子和连接到可变电阻元件的第二输入端子电流发生器，并且被配置为比较第一输入端子和第二输入端子的电流。

38. 发明申请

US20130029257A1 THERMOCHROMIC COLOR-MEMORIZATION TONER, CARTRIDGE INCLUDING SAME HOUSED THEREIN, IMAGE FORMATION APPARATUS, CARTRIDGE SET, AND IMAGE FORMATION APPARATUS SET 有权
标题翻译：热变色彩记忆墨粉盒，包括同类住房的图像，图像形成装置，墨盒和图像形成装置
公开(公告)号：US20130029257A1
公开(公告)日：2013-01-31
申请号：US13509663
申请日：2009-11-13
申请人： Katsuyuki Fujita , Yoshiaki Ono , Yutaka Shibahashi
发明人： Katsuyuki Fujita , Yoshiaki Ono , Yutaka Shibahashi
IPC分类号： G03G9/00 , G03G15/08
CPC分类号： G03G9/0812 , C09D11/17 , G03G9/0821 , G03G9/0825 , G03G9/0926 , G03G9/0928
摘要： The present invention relates to a thermochromic color-memory toner containing: a microcapsule pigment encapsulating a thermochromic color-memory composition; and a binder resin, in which the microcapsule pigment shows a hysteresis characteristic that, in a temperature-rise process, decoloration starts when the temperature reaches t3 and the pigment completely reaches a decolored state in a temperature region of t4 or higher, and in a temperature-drop process, coloration starts when the temperature reaches t2 and the pigment completely reaches a colored state in a temperature region of ti or lower, and ti is in a range of from −50 to 0° C. and t4 is in a range of from 50 to 150° C.
摘要翻译：本发明涉及一种热致变色彩记忆调色剂，其含有：包封热变色色记忆组合物的微胶囊颜料; 和粘合剂树脂，其中微胶囊颜料显示出在温度升高过程中当温度达到t3时开始脱色并且颜料在t4或更高的温度区域完全达到脱色状态的滞后特性，并且在温度下降过程中，当温度达到t2时开始着色，并且颜料在ti或更低的温度区域中完全达到着色状态，并且t 1在-50至0℃的范围内，并且t 4在一定范围内为50〜150℃

39. 发明授权

US08173052B2 Writing implement with thermochromic coloring color-memory composition 有权
标题翻译：书写工具用热致色色彩记忆组合
公开(公告)号：US08173052B2
公开(公告)日：2012-05-08
申请号：US12846238
申请日：2010-07-29
申请人： Katsuyuki Fujita
发明人： Katsuyuki Fujita
IPC分类号： B05C21/00 , B43K7/00 , B43L19/00 , G02F1/361
CPC分类号： B41M5/305 , B41M5/165 , B41M5/3375 , C09B67/0013 , C09D5/26 , C09D11/037 , C09D11/17 , C09D11/18 , C09K9/02 , C09K2211/1014
摘要： A writing implement with a thermochromic coloring color-memory composition which comprises a homogeneous solubilized mixture of (A) an electron donative coloring organic compound, (B) an electron accepting compound and (C) a reaction medium which controls color reactions of the components (A) and (B), wherein a complete decoloring temperature (T4) of the thermochromic coloring color-memory composition is 50° C. or higher and a coloring starting temperature (T2) of thermochromic coloring color-memory composition is 10° C. or lower regarding the color density-temperature curve, and the thermochromic coloring color-memory composition has color-memory ability at the ordinary temperature range.
摘要翻译：一种具有热致变色着色记录组合物的书写工具，其包含（A）电子给体着色有机化合物，（B）电子接受化合物和（C）控制组分的着色反应的反应介质的均匀溶解混合物（（A）和（B），其中，所述热致变色着色色记忆组合物的完全脱色温度（T4）为50℃以上，所述着色着色色记忆组合物的着色开始温度（T2）为10℃。或更低，并且热致变色着色色记忆组合物在常温范围内具有记忆能力。

40. 发明申请

US20120063216A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120063216A1
公开(公告)日：2012-03-15
申请号：US13205094
申请日：2011-08-08
申请人： Katsuyuki Fujita , Yoshihiro Ueda
发明人： Katsuyuki Fujita , Yoshihiro Ueda
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C5/025 , G11C7/14 , G11C8/08 , G11C11/1659 , G11C11/1675
摘要： A memory includes bit lines, word lines, and memory cells connected between first and second BLs. The cells arranged in an extending direction of the BLs constitute columns. The second BL is shared between two columns. The cells in a first pair of columns are arranged to be shifted in the extending direction of the BLs by a half-pitch from the cells in a second pair of columns. The device includes a dummy cell having an equal distance from the adjacent memory elements. Further, the device includes a row decoder driving the cells in the first pair of columns by driving paired word lines, and driving the cells in the second pair of columns by driving paired word lines. Each cell includes selection transistors. The selection transistors are connected in parallel between the memory element and the first BL. Gates of the transistors are connected to different WLs.
摘要翻译：存储器包括连接在第一和第二BL之间的位线，字线和存储单元。布置在BL的延伸方向上的单元构成列。第二个BL在两列之间共享。第一对列中的单元布置成沿着第二对列中的单元在BL的延伸方向上以半间距移位。该装置包括与相邻存储元件具有相等距离的虚拟单元。此外，该装置包括行解码器，通过驱动配对字线来驱动第一对列中的单元，并且通过驱动配对字线来驱动第二对列中的单元。每个单元包括选择晶体管。选择晶体管并联连接在存储元件和第一BL之间。晶体管的栅极连接到不同的WL。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式