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31. 发明授权

US07151702B2 High voltage generators having an integrated discharge path for use in non-volatile semiconductor memory devices 有权
标题翻译：具有用于非易失性半导体存储器件的集成放电路径的高压发生器
公开(公告)号：US07151702B2
公开(公告)日：2006-12-19
申请号：US10915294
申请日：2004-08-10
申请人： Wook-Ghee Han , Dae-Seok Byeon , Sung-Soo Lee , Young-Ho Lim
发明人： Wook-Ghee Han , Dae-Seok Byeon , Sung-Soo Lee , Young-Ho Lim
IPC分类号： G11C5/14
CPC分类号： G11C16/12 , G11C5/145
摘要： High voltage generators include a charge pump and a ripple reduction circuit that includes an integrated discharge path. The ripple reduction circuit limits the voltage level from a charge pump when the charge pump is in a first operating mode and provides a discharge path that from the output terminal of the ripple reduction circuit to the output of the charge pump when the charge pump is in a second operating mode. Semiconductor memories incorporating such high voltage generators are also provided. Coupling circuits having an integrated discharge path are also provided.
摘要翻译：高压发生器包括电荷泵和包括集成放电路径的纹波降低电路。当电荷泵处于第一操作模式时，纹波降低电路限制来自电荷泵的电压电平，并且当电荷泵处于第一操作模式时提供从脉动降低电路的输出端子到电荷泵的输出的放电路径第二种操作模式。还提供了包括这种高电压发生器的半导体存储器。还提供具有集成放电路径的耦合电路。

32. 发明申请

US20060279999A1 Methods of Erasing Flash Memory Devices by Applying Wordline Bias Voltages Having Multiple Levels and Related Flash Memory Devices 有权
标题翻译：通过应用具有多个级别的字线偏置电压和相关闪存器件来擦除闪存器件的方法
公开(公告)号：US20060279999A1
公开(公告)日：2006-12-14
申请号：US11381556
申请日：2006-05-04
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： Methods of erasing data in a flash memory device are provided in which a plurality of wordline bias voltages are generated that include wordline bias voltages having at least two different levels, erasing data by applying the different wordline bias voltages to respective ones of a plurality of wordlines while applying an erasing voltage to a bulk region of memory cells, and verifying the erased states of the memory cells. Pursuant to these methods, the spread of the threshold-voltage distribution profile that may result from deviations of erasure-coupling ratios between memory cells may be reduced.
摘要翻译：提供擦除闪速存储器件中的数据的方法，其中产生多个字线偏置电压，其包括具有至少两个不同电平的字线偏置电压，通过将不同的字线偏置电压施加到多个字线中的相应字线来擦除数据同时将擦除电压施加到存储器单元的主体区域，以及验证存储器单元的擦除状态。根据这些方法，可能会降低可能由存储器单元之间的擦除耦合比的偏差导致的阈值 - 电压分布曲线的扩展。

33. 发明授权

US07110292B2 Programming circuits and methods for multimode non-volatile memory devices 有权
公开(公告)号：US07110292B2
公开(公告)日：2006-09-19
申请号：US11020517
申请日：2004-12-22
申请人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Sung-Soo Lee , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/30 , G11C2211/5641
摘要： A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

34. 发明申请

US20050128821A1 High-voltage generator circuit and semiconductor memory device including the same 有权
标题翻译：高压发生器电路和包括其的半导体存储器件
公开(公告)号：US20050128821A1
公开(公告)日：2005-06-16
申请号：US10977426
申请日：2004-10-28
申请人： Jong-Hwa Kim , Dae-Seok Byeon
发明人： Jong-Hwa Kim , Dae-Seok Byeon
IPC分类号： G11C16/06 , G11C5/14 , G11C11/407 , H01L27/10 , H02M3/07 , G11C5/00
CPC分类号： H02M3/073 , H02M2001/0041
摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.
摘要翻译：根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。分压器通过分压高电压在输出节点产生分压。放电部分响应于第一控制信号将高电压放电到电源电压。比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。

35. 发明授权

US06717857B2 Non-volatile semiconductor memory device with cache function and program, read, and page copy-back operations thereof 有权
标题翻译：具有缓存功能和程序，读取和页面复制操作的非易失性半导体存储器件
公开(公告)号：US06717857B2
公开(公告)日：2004-04-06
申请号：US10279386
申请日：2002-10-23
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C1134
CPC分类号： G11C16/10 , G06F12/0893 , G06F2212/2022 , G06F2212/3042 , G11C16/26 , G11C2216/14
摘要： A non-volatile memory device according to embodiments of the invention includes a page buffer acting as a sense amplifier during a read operation and as a write driver during a program operation. The page buffer has two sense and latch blocks, which exclusively carry out the same function. While one of the sense and latch blocks carries out a read operation, the other sense and latch block outputs previously sensed data to the exterior. Further, while one of the sense and latch blocks carries out a program operation, the other sense and latch block loads data to be programmed. Due to the page buffer, an operation speed of the non-volatile memory device can be enhanced.
摘要翻译：根据本发明的实施例的非易失性存储器件包括在读取操作期间用作读出放大器的页缓冲器，以及在编程操作期间作为写驱动器。页面缓冲区具有两个感测和锁存块，它们独有地执行相同的功能。虽然其中一个感测和锁存块执行读取操作，但另一个感测和锁存块将先前感测的数据输出到外部。此外，当感测和锁存块中的一个执行编程操作时，另一个感测和锁存块加载待编程的数据。由于页面缓冲器，可以提高非易失性存储器件的操作速度。

36. 发明申请

US20170168742A1 MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING MEMORY DEVICE 审中-公开
公开(公告)号：US20170168742A1
公开(公告)日：2017-06-15
申请号：US15443647
申请日：2017-02-27
申请人： SANG-WAN NAM , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
发明人： SANG-WAN NAM , Doo-Hyun Kim , Dae-Seok Byeon , Chi-Weon Yoon
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/061 , G06F3/0644 , G06F3/0655 , G06F3/0688 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/16 , G11C16/26 , G11C16/34 , G11C16/3459 , H01L27/11582
摘要： A memory device is provided as follows. A memory cell region includes a plurality of blocks, each block including a plurality of NAND strings. A control logic divides the plurality of blocks into a plurality of block regions based on a smaller distance of a first distance with respect to a first edge of the memory cell region and a second distance with respect to a second edge of the memory cell region and controls an operation performed on the memory cell region using a plurality of bias sets of operation parameters for the operation. Each bias set is associated with one of the block regions.

37. 发明授权

US09646687B2 Resistive memory device and operating method 有权
公开(公告)号：US09646687B2
公开(公告)日：2017-05-09
申请号：US14619992
申请日：2015-02-11
申请人： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
发明人： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
IPC分类号： G06F11/07 , G11C13/00 , G11C29/52
CPC分类号： G11C13/0033 , G06F11/073 , G06F11/0751 , G06F11/0793 , G06F11/1048 , G11C13/0035 , G11C13/0069 , G11C29/52 , G11C2013/0092 , G11C2213/77
摘要： Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.

38. 发明授权

US08218371B2 Multi-bit flash memory device and method of analyzing flag cells of the same 有权
标题翻译：多位闪存器件及其分析标志单元的方法
公开(公告)号：US08218371B2
公开(公告)日：2012-07-10
申请号：US12467529
申请日：2009-05-18
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C11/5621 , G11C2211/5646
摘要： Disclosed is a multi-bit flash memory device which includes a memory cell array and a control circuit. The memory cell array has multiple memory cells and multiple flag cells. The control circuit determines whether the flag cells are programmed, based on a reference corresponding to a read margin of the flag cells, and controls a program operation of the memory cells in response to the determination.
摘要翻译：公开了一种包括存储单元阵列和控制电路的多位闪存装置。存储单元阵列具有多个存储单元和多个标志单元。控制电路基于与标志单元的读取余量相对应的基准来确定标志单元是否被编程，并且响应于该确定来控制存储器单元的编程操作。

39. 发明授权

US07911850B2 Method of programming flash memory device 有权
标题翻译：闪存设备编程方法
公开(公告)号：US07911850B2
公开(公告)日：2011-03-22
申请号：US12489641
申请日：2009-06-23
申请人： Dong-Hyuk Chae , Dae-Seok Byeon
发明人： Dong-Hyuk Chae , Dae-Seok Byeon
IPC分类号： G11C16/12 , G11C16/08
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08
摘要： Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.
摘要翻译：闪速存储器件包括其中具有多个EEPROM串的NAND串的存储器阵列。提供字线驱动程序以提高编程效率。字线驱动器通过多个字线电耦合到存储器阵列。字线驱动器包括多个通过电压开关。这些开关具有由二极管电耦合到多个字线的输出。编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

40. 发明授权

US07898871B2 Flash memory device operating at multiple speeds 有权
公开(公告)号：US07898871B2
公开(公告)日：2011-03-01
申请号：US11853958
申请日：2007-09-12
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/06
CPC分类号： G11C16/30 , G11C16/24
摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.

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