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1. 发明申请

US20050128821A1 High-voltage generator circuit and semiconductor memory device including the same 有权
标题翻译：高压发生器电路和包括其的半导体存储器件
公开(公告)号：US20050128821A1
公开(公告)日：2005-06-16
申请号：US10977426
申请日：2004-10-28
申请人： Jong-Hwa Kim , Dae-Seok Byeon
发明人： Jong-Hwa Kim , Dae-Seok Byeon
IPC分类号： G11C16/06 , G11C5/14 , G11C11/407 , H01L27/10 , H02M3/07 , G11C5/00
CPC分类号： H02M3/073 , H02M2001/0041
摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.
摘要翻译：根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。分压器通过分压高电压在输出节点产生分压。放电部分响应于第一控制信号将高电压放电到电源电压。比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。

2. 发明授权

US07154789B2 High-voltage generator circuit and semiconductor memory device including the same 有权
标题翻译：高压发生器电路和包括其的半导体存储器件
公开(公告)号：US07154789B2
公开(公告)日：2006-12-26
申请号：US10977426
申请日：2004-10-28
申请人： Jong-Hwa Kim , Dae-Seok Byeon
发明人： Jong-Hwa Kim , Dae-Seok Byeon
IPC分类号： G11C5/14
CPC分类号： H02M3/073 , H02M2001/0041
摘要： According to embodiments of the invention, a high-voltage generator circuit may include a voltage detector block that has a voltage divider, a discharge section, a comparator, and a control signal generator. The voltage divider generates a divided voltage at an output node by dividing a high voltage. The discharge section discharges the high voltage to a power voltage in response to a first control signal. The comparator determines whether the divided voltage reaches a reference voltage, and the control signal generator generates a second control signal in response to an output from the comparator and the first control signal. The voltage divider may include a high-voltage prevention circuit that prevents the high voltage from being applied to a low-voltage transistor of the comparator during a discharge period of the high voltage. The high-voltage prevention circuit may include a depletion-type or enhancement-type NMOS transistor having a high breakdown voltage.
摘要翻译：根据本发明的实施例，高压发生器电路可以包括具有分压器，放电部分，比较器和控制信号发生器的电压检测器块。分压器通过分压高电压在输出节点产生分压。放电部分响应于第一控制信号将高电压放电到电源电压。比较器确定分压是否达到参考电压，并且控制信号发生器响应于比较器的输出和第一控制信号产生第二控制信号。分压器可以包括高电压防止电路，其在高电压的放电期间防止高电压施加到比较器的低压晶体管。高压防止电路可以包括具有高击穿电压的耗尽型或增强型NMOS晶体管。

3. 发明授权

US09899394B2 Vertical memory devices having contact plugs contacting stacked gate electrodes 有权
公开(公告)号：US09899394B2
公开(公告)日：2018-02-20
申请号：US15001877
申请日：2016-01-20
申请人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
发明人： Sung-Min Hwang , Jee-Yong Kim , Dae-Seok Byeon
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/11575 , H01L27/11573 , H01L27/11565 , H01L27/1157 , H01L27/11563 , H01L27/11582
CPC分类号： H01L27/115 , H01L27/11563 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L27/11582
摘要： A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

4. 发明授权

US09355721B2 Resistive memory device and operating method 有权
标题翻译：电阻式存储器件及操作方法
公开(公告)号：US09355721B2
公开(公告)日：2016-05-31
申请号：US14800727
申请日：2015-07-16
申请人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
发明人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要翻译：操作存储器件的方法包括：通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压在第二设定写入间隔期间到第一信号线的第二电压。

5. 发明授权

US07957201B2 Flash memory device operating at multiple speeds 有权
标题翻译：闪存设备以多种速度运行
公开(公告)号：US07957201B2
公开(公告)日：2011-06-07
申请号：US12854987
申请日：2010-08-12
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/30 , G11C16/24
摘要： A method of operating a flash memory device includes a first operating mode and a second operating mode having different operating speeds. Each one of the first and second operating modes includes a bit line set-up interval and at least one additional interval. The flash memory is divided into first and second mats connected to respective first and second R/W circuits. During the bit line set-up interval of the second operating mode, the flash memory controls operation of both the first and second R/W circuits in a time division approach to stagger respective peak current intervals for the first and second mats.
摘要翻译：操作闪速存储器件的方法包括具有不同操作速度的第一操作模式和第二操作模式。第一和第二操作模式中的每一个包括位线建立间隔和至少一个附加间隔。闪存被分成连接到相应的第一和第二R / W电路的第一和第二垫。在第二操作模式的位线设置间隔期间，闪速存储器以时分方式控制第一和第二R / W电路的操作，以交错第一和第二垫的相应的峰值电流间隔。

6. 发明授权

US07852682B2 Flash memory device and program method of flash memory device using different voltages 有权
标题翻译：闪存器件和使用不同电压的闪存器件的程序方法
公开(公告)号：US07852682B2
公开(公告)日：2010-12-14
申请号：US11830260
申请日：2007-07-30
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10
摘要： A flash memory and a program method of the flash memory include applying a pass voltage to word lines to boost a channel voltage, which is discharged to a ground voltage. A program voltage is applied to a selected word line and a local voltage is applied to at least one word line supplied with the pass voltage while the program voltage is being applied to the selected word line. The local voltage is lower than the pass voltage and equal to or higher than the ground voltage. The boosted channel voltage may be discharged before the program voltage is applied to the selected word line.
摘要翻译：闪速存储器和闪速存储器的编程方法包括对字线施加通过电压以升高被释放到接地电压的通道电压。一个编程电压被施加到所选择的字线，并且当编程电压被施加到所选择的字线时，局部电压被施加到提供有通过电压的至少一个字线。局部电压低于通过电压，等于或高于接地电压。在将编程电压施加到所选择的字线之前，升压的通道电压可以被放电。

7. 发明授权

US07529134B2 Flash memory devices configured to be programmed using variable initial program loops and related devices 有权
标题翻译：配置为使用可变初始程序循环和相关设备编程的闪存设备
公开(公告)号：US07529134B2
公开(公告)日：2009-05-05
申请号：US11439797
申请日：2006-05-24
申请人： Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
发明人： Wook-Ghee Hahn , Young-Ho Lim , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/30 , G11C5/145 , G11C8/08 , G11C16/04 , G11C16/08 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： A method of programming a nonvolatile memory device including a plurality of memory cells includes providing a plurality of program loops having a corresponding plurality of program voltages associated therewith. A first one of the plurality of program loops is activated to generate a first program voltage to program a first one of the plurality of memory cells. A second one of the plurality of program loops is activated to generate a second program voltage to program a second one of the plurality of memory cells.
摘要翻译：包括多个存储器单元的非易失性存储器件的编程方法包括提供具有与其相关联的相应多个编程电压的多个程序循环。多个程序循环中的第一个被激活以产生第一编程电压以编程多个存储器单元中的第一个。多个程序循环中的第二个程序循环被激活以产生第二编程电压以编程多个存储器单元中的第二个。

8. 发明申请

US20090021985A1 INTERNAL VOLTAGE GENERATOR AND CONTROL METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：内部电压发生器及其控制方法及其半导体存储器件及其系统
公开(公告)号：US20090021985A1
公开(公告)日：2009-01-22
申请号：US12175494
申请日：2008-07-18
申请人： Dae-Seok Byeon
发明人： Dae-Seok Byeon
IPC分类号： G11C16/06 , G11C7/00 , G11C5/14
CPC分类号： G11C29/02 , G11C5/147 , G11C16/30 , G11C29/021 , G11C29/028
摘要： An internal voltage of a semiconductor memory device is controlled, where the internal voltage is set according to a reference voltage. The reference voltage is controlled according to first control data to increase the internal voltage to be higher than a target voltage in a power-up operation, and second control data is read. The reference voltage is then controlled according to the second control data to decrease the internal voltage to the target voltage.
摘要翻译：控制半导体存储器件的内部电压，其中根据参考电压设置内部电压。根据第一控制数据控制参考电压，以在上电操作中将内部电压增加到高于目标电压，并且读取第二控制数据。然后根据第二控制数据控制参考电压，以将内部电压降低到目标电压。

9. 发明申请

US20080123417A1 Semiconductor device including a high voltage generation circuit and method of a generating high voltage 有权
公开(公告)号：US20080123417A1
公开(公告)日：2008-05-29
申请号：US11605227
申请日：2006-11-29
申请人： Dae-Seok Byeon , Young-Ho Lim
发明人： Dae-Seok Byeon , Young-Ho Lim
IPC分类号： G11C16/04 , G05F1/10 , G11C8/10
CPC分类号： G11C16/30 , G11C5/145 , G11C8/10 , G11C16/0483 , G11C16/08 , H02M3/07
摘要： A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response to the first pump clock signal. The device also comprises a second pump clock generator configured to generate a second pump clock signal based on the first pump output voltage. The device also comprises a second charge pump configured to generate a second pump output voltage in response to the second pump clock signal. The device also comprises a third pump clock generator configured to generate a third pump clock signal based on the first power supply voltage. The device also comprises a third charge pump configured to generate a third pump output voltage in response to the third pump clock signal.

10. 发明申请

US20060133145A1 Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats 有权
公开(公告)号：US20060133145A1
公开(公告)日：2006-06-22
申请号：US11283646
申请日：2005-11-21
申请人： Jin-Sung Park , Dae-Seok Byeon
发明人： Jin-Sung Park , Dae-Seok Byeon
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C2216/14
摘要： A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat.

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