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1. 发明授权

US09646687B2 Resistive memory device and operating method 有权
公开(公告)号：US09646687B2
公开(公告)日：2017-05-09
申请号：US14619992
申请日：2015-02-11
申请人： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
发明人： Hyo-Jin Kwon , Yeong-Taek Lee , Dae-Seok Byeon , Yong-Kyu Lee , Hyun-Kook Park
IPC分类号： G06F11/07 , G11C13/00 , G11C29/52
CPC分类号： G11C13/0033 , G06F11/073 , G06F11/0751 , G06F11/0793 , G06F11/1048 , G11C13/0035 , G11C13/0069 , G11C29/52 , G11C2013/0092 , G11C2213/77
摘要： Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.

2. 发明授权

US09406359B2 Memory devices, memory systems, and related operating methods 有权
标题翻译：存储器件，存储器系统和相关操作方法
公开(公告)号：US09406359B2
公开(公告)日：2016-08-02
申请号：US14683186
申请日：2015-04-10
申请人： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Chi-Weon Yoon
发明人： Hyun-Kook Park , Yeong-Taek Lee , Dae-Seok Byeon , Chi-Weon Yoon
IPC分类号： G11C29/52 , G11C7/22 , G06F11/07 , G11C7/06 , G11C7/10 , G11C7/14 , G11C11/56 , G11C13/00 , G11C29/02 , G11C29/42 , G11C7/12
CPC分类号： G11C7/22 , G06F11/073 , G06F11/076 , G11C7/062 , G11C7/067 , G11C7/1045 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/004 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2013/0054 , G11C2213/72
摘要： A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
摘要翻译：一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

3. 发明授权

US09570170B2 Resistive memory device and method of operating the same 有权
标题翻译：电阻式存储器件及其操作方法
公开(公告)号：US09570170B2
公开(公告)日：2017-02-14
申请号：US14839606
申请日：2015-08-28
申请人： Chi-Weon Yoon , Hyun-Kook Park , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee
发明人： Chi-Weon Yoon , Hyun-Kook Park , Yeong-Taek Lee , Bo-Geun Kim , Yong-Kyu Lee
IPC分类号： G11C8/00 , G11C13/00 , G11C11/56 , G11C11/16
CPC分类号： G11C13/0069 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/5607 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0028 , G11C13/004 , G11C2213/72
摘要： A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.
摘要翻译：存储器件包括具有分别布置在第一信号线与第二信号线交叉的区域中的多个存储单元的存储单元阵列。存储装置还包括具有分别连接到第一信号线的多个线路选择开关单元的解码器。多个线路选择开关单元中的每一个选择性地响应于第一开关信号和彼此不同的第二开关信号的第一信号线施加偏置电压到对应于多个线路选择开关单元中的每一个的第一信号线处于激活状态。

4. 发明授权

US09478285B2 Cross-point memory device including multi-level cells and operating method thereof 有权
标题翻译：包括多电平电池的交叉点存储器件及其操作方法
公开(公告)号：US09478285B2
公开(公告)日：2016-10-25
申请号：US14800060
申请日：2015-07-15
申请人： Hyun-Kook Park , Chi-Weon Yoon , Dae-Seok Byeon
发明人： Hyun-Kook Park , Chi-Weon Yoon , Dae-Seok Byeon
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56 , G11C11/16
CPC分类号： G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5642 , G11C13/0002 , G11C2013/0054 , G11C2213/71
摘要： A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.
摘要翻译：一种操作具有多电平单元阵列的交叉点存储器件的方法包括通过多个感测操作执行关于多电平单元的第一读取操作，以确定第一状态并执行关于第二读取操作的第二读取操作所述多电平单元通过多个感测操作来确定第二状态。在第一读取操作中使用的第一电压的电平与在第一读取操作中的第二感测操作中使用的第二电压的电平之间的差异不同于在第一感测中使用的第三电压的电平之间的差操作和在第二读取操作中的第二感测操作中使用的第四电压的电平。

5. 发明授权

US09355721B2 Resistive memory device and operating method 有权
标题翻译：电阻式存储器件及操作方法
公开(公告)号：US09355721B2
公开(公告)日：2016-05-31
申请号：US14800727
申请日：2015-07-16
申请人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
发明人： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
IPC分类号： G11C11/34 , G11C16/04 , G11C13/00
CPC分类号： G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
摘要： A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
摘要翻译：操作存储器件的方法包括：通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压在第二设定写入间隔期间到第一信号线的第二电压。

6. 发明授权

US09589632B2 Resistive memory device including column decoder and method of performing a bidirectional driving operation and providing appropriate biasing with respect to bit lines 有权
标题翻译：电阻式存储器件包括列译码器和执行双向驱动操作并提供相对于位线的适当偏置的方法
公开(公告)号：US09589632B2
公开(公告)日：2017-03-07
申请号：US14820197
申请日：2015-08-06
申请人： Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
发明人： Hyun-Kook Park , Chi-Weon Yoon , Yeong-Taek Lee
IPC分类号： G11C11/00 , G11C13/00 , G11C11/16 , G11C11/22
CPC分类号： G11C13/0026 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/2255 , G11C13/0028 , G11C13/004 , G11C13/0069
摘要： A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.
摘要翻译：一种电阻式存储装置，包括具有第一开关单元的列解码器，该第一开关单元包括对应于多条信号线中的每一条布置的至少一对开关，以及第二开关单元，该第二开关单元包括对应于至少第一开关单元的一对开关。第一开关单元的第一对开关包括相同类型的第一开关和第二开关，第二开关单元的第二对开关包括第三开关和第四开关，第三开关和第四开关连接到第一开关一对开关通过穿过第一开关将选择电压提供给第一信号线，并且通过选择性地通过第一开关或第二开关将第一信号线提供禁止电压。

7. 发明授权

US09443586B2 Nonvolatile memory device, memory system including the same and method for driving nonvolatile memory device 有权
标题翻译：非易失性存储器件，包括相同的存储器系统和用于驱动非易失性存储器件的方法
公开(公告)号：US09443586B2
公开(公告)日：2016-09-13
申请号：US14680496
申请日：2015-04-07
申请人： Hyun-Kook Park
发明人： Hyun-Kook Park
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C2213/71 , G11C2213/72
摘要： A nonvolatile memory device can improve a read retry operation speed while minimizing a reduction in the capability of a memory read operation by performing a read retry operation. The nonvolatile memory device includes a resistive memory cell, a sensing node, and a sense amplifier connected to the sensing node and sensing a difference between a voltage level of the sensing node and a reference voltage level or a difference between a current level of the sensing node and a reference current level. When a read fail bit value is generated during a read operation of data stored in the resistive memory cell, a current flowing in the resistive memory cell is changed by changing a difference between voltages of opposite ends of the resistive memory cell and a read retry operation is then performed.
摘要翻译：非易失性存储器件可以通过执行读取重试操作来最小化存储器读取操作的能力，从而提高读取重试操作速度。非易失性存储器件包括电阻存储器单元，感测节点和连接到感测节点的感测放大器，并感测感测节点的电压电平与参考电压电平之间的差值，或感测节点的当前电平之间的差值节点和参考电流水平。当在存储在电阻性存储单元中的数据的读取操作期间产生读取失败位值时，通过改变电阻性存储单元的相对端的电压和读取重试操作之间的差异来改变在电阻性存储单元中流动的电流然后执行。

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