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31. 发明授权

US06420241B2 Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process 失效
标题翻译：用于在半导体器件中形成隔离区域的方法以及使用两步氧化工艺得到的结构
公开(公告)号：US06420241B2
公开(公告)日：2002-07-16
申请号：US09062291
申请日：1998-04-17
申请人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
发明人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
IPC分类号： H01L2176
CPC分类号： H01L21/76221
摘要： A method for forming an element isolation film of a semiconductor device and the semiconductor device. A pad insulator is constructed on a semiconductor substrate. An over-etching process is performed to recess the semiconductor substrate to a predetermined depth while giving a pad insulator pattern. After an insulator spacer is formed at the side wall of the pad insulator pattern, the exposed region of the semiconductor substrate is thermally oxidized to grow an oxide which is, then, removed to form a recess. An element isolation film is formed in the recess by break-through field oxidation and high temperature field oxidation. The element isolation film thus obtained can prevent the field oxide “ungrowth” phenomenon and at the same time mitigate the field oxide thinning effect as well as improve the properties of the gate oxide.
摘要翻译：一种用于形成半导体器件的元件隔离膜和半导体器件的方法。衬垫绝缘体构造在半导体衬底上。执行过蚀刻处理以将半导体衬底凹入预定深度，同时给出衬垫绝缘体图案。在衬垫绝缘体图案的侧壁上形成绝缘体间隔物之后，半导体衬底的暴露区域被热氧化以生长氧化物，然后被去除以形成凹部。元件隔离膜通过穿透场氧化和高温场氧化在凹陷中形成。由此获得的元件隔离膜可以防止场氧化物“不生长”现象，同时减轻场氧化物稀化效应以及改善栅极氧化物的性质。

32. 发明授权

US06417055B2 Method for forming gate electrode for a semiconductor device 有权
标题翻译：用于形成半导体器件的栅电极的方法
公开(公告)号：US06417055B2
公开(公告)日：2002-07-09
申请号：US09895295
申请日：2001-07-02
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/665
摘要： The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.
摘要翻译：本发明涉及在接触形成处理中更容忍未对准的半导体器件中形成栅电极的方法。改进的栅极结构减少了栅电极和随后形成的导体（例如DRAM位线和存储线）之间的短路的形成。栅电极由具有相邻绝缘间隔物的镶嵌金属栅电极形成，部分蚀刻金属栅电极以形成沟槽; 沉积氮化物膜; 并蚀刻氮化物膜以在栅电极的外部部分上形成附加的保护绝缘体。通过这些保护绝缘子到位，随后的接触处理变得更加容忍不对准，减少返工和提高产量。

33. 发明授权

US06387788B2 Method for forming polycide gate electrode of metal oxide semiconductor field effect transistor 失效
标题翻译：用于形成金属氧化物半导体场效应晶体管的多晶硅栅电极的方法
公开(公告)号：US06387788B2
公开(公告)日：2002-05-14
申请号：US09343171
申请日：1999-06-29
申请人： Se Aug Jang , In Seok Yeo
发明人： Se Aug Jang , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L21/28247 , Y10S438/926
摘要： The present invention provides a method for fabricating an improved gate electrode of a MOSFET device. And the method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied comprises the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen atmosphere.
摘要翻译：本发明提供一种用于制造MOSFET器件的改进的栅电极的方法。并且制造具有施加了硅化钛的多晶硅栅极的MOSFET器件的方法包括以下步骤：依次在栅绝缘层和钛层上依次形成多晶硅层，在钛层上形成覆盖层，通过在氮气气氛中进行快速热处理形成硅化钛层。

34. 发明授权

US06303494B1 Method of forming gate electrode in semiconductor device 失效
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06303494B1
公开(公告)日：2001-10-16
申请号：US09460815
申请日：1999-12-14
申请人： In Seok Yeo , Se Aug Jang
发明人： In Seok Yeo , Se Aug Jang
IPC分类号： H01L2708
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/28247
摘要： A method of forming a gate electrode in a semiconductor device which can effectively prevent abnormal oxidation of a metal layer without occurring thermal budget and the deterioration of a gate insulating layer during gate re-oxidation process, is disclosed. In the present invention, one selected from a group consisting of an iridium(Ir) layer, a ruthenium(Ru) layer and an osmium(Os) layer capable of forming a nonvolatile conductive metal oxide layer, is used as a metal layer of a gate electrode instead of a W layer in conventional art. Therefore, although a gate re-oxidation process is performed by a well known method, it is effectively prevented that the metal layer is abnormally oxidized, thereby forming an uniform oxide layer on the side wall of the gate. Furthermore, since the oxide layer is conductive, the resistivity of the gate electrode is reduced.
摘要翻译：公开了一种在半导体器件中形成栅电极的方法，其可以有效地防止金属层的异常氧化而不发生热预算，并且在栅极再氧化处理期间栅极绝缘层的劣化。在本发明中，使用从能够形成非挥发性导电金属氧化物层的铱（Ir）层，钌（Ru）层和锇（Os）层组成的组中的一种作为金属层栅电极而不是常规技术中的W层。因此，虽然通过公知的方法进行栅极再氧化处理，但是有效地防止金属层异常氧化，从而在栅极的侧壁上形成均匀的氧化物层。此外，由于氧化物层是导电的，所以栅电极的电阻率降低。

35. 发明授权

US06248632B1 Method of forming gate electrode with polycide structure in semiconductor device 有权
标题翻译：在半导体器件中形成具有聚硅氧烷结构的栅电极的方法
公开(公告)号：US06248632B1
公开(公告)日：2001-06-19
申请号：US09459510
申请日：1999-12-13
申请人： Se Aug Jang , Heung Jae Cho
发明人： Se Aug Jang , Heung Jae Cho
IPC分类号： H01L21336
CPC分类号： H01L29/4941 , H01L21/28052
摘要： A method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer, is disclosed. According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions (N2+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.
摘要翻译：公开了一种在可以改善多晶硅层和硅层之间的界面粗糙度的半导体器件中形成具有聚硅氧烷结构的栅电极的方法。根据本发明，在半导体衬底上形成栅绝缘层上的栅绝缘层和掺杂多晶硅层。然后通过将氮离子（N 2 +）离子注入到多晶硅层的表面中或通过在含氮气体的气氛下热处理多晶硅的表面，在多晶硅层的表面上形成含氮多晶硅层。接着，在氮多晶硅层上形成金属硅化物层。此后，依次蚀刻金属硅化物层，氮多晶硅层和多晶硅层以形成栅电极。

36. 发明授权

US6027985A Method for forming element isolating film of semiconductor device 有权
标题翻译：半导体器件元件隔离膜的形成方法
公开(公告)号：US6027985A
公开(公告)日：2000-02-22
申请号：US252675
申请日：1999-02-22
申请人： Se Aug Jang , Tae Sik Song , Young Bog Kim , Byung Jin Cho , Jong Choul Kim
发明人： Se Aug Jang , Tae Sik Song , Young Bog Kim , Byung Jin Cho , Jong Choul Kim
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76205 , H01L21/7621 , H01L21/76221
摘要： A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices. The method includes the steps of sequentially forming a pad oxide film and a first nitride film over a semiconductor substrate, over-etching the first nitride film and the pad oxide film by use of an element isolating mask, thereby forming a first hole in the semiconductor substrate, cleaning the entire upper surface of the resulting structure by use of an etch solution, forming second-nitride film spacers on side walls of the selectively etched first nitride film, pad oxide film and first hole, forming a second hole in the first hole of the semiconductor substrate by use of the first nitride film and second-nitride film spacers as a mask, thermally oxidizing the surface of the second hole, thereby forming a thermal oxide film, and removing the first nitride film, pad oxide film and second-nitride film spacers, thereby forming an element isolating film.
摘要翻译：一种用于形成半导体器件的元件隔离膜的方法，其能够实现拓扑的减小和鸟喙现象的发生的减少，使得可以容易地执行后续处理以制造高度集成的半导体器件。该方法包括以下步骤：在半导体衬底上顺序地形成衬垫氧化膜和第一氮化物膜，通过使用元件隔离掩模对第一氮化物膜和衬垫氧化膜进行过蚀刻，从而在半导体中形成第一孔衬底，通过使用蚀刻溶液清洁所得结构的整个上表面，在选择性蚀刻的第一氮化物膜，衬垫氧化物膜和第一孔的侧壁上形成第二氮化物膜间隔物，在第一孔中形成第二孔通过使用第一氮化物膜和第二氮化物膜间隔物作为掩模，对第二孔的表面进行热氧化，从而形成热氧化膜，并除去第一氮化物膜，衬垫氧化物膜和第二氮化物膜，氮化物膜间隔物，从而形成元件隔离膜。

37. 发明授权

US6013561A Method for forming field oxide film of semiconductor device 失效
标题翻译：半导体器件场氧化膜形成方法
公开(公告)号：US6013561A
公开(公告)日：2000-01-11
申请号：US961132
申请日：1997-10-30
申请人： Se Aug Jang , Byung Jin Cho , Jong Choul Kim
发明人： Se Aug Jang , Byung Jin Cho , Jong Choul Kim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76205
摘要： A method for forming a field oxide film of a highly integrated semiconductor device, in which an annealing step is carried out during a field oxide film formation step for growing the field oxide film adapted to isolate elements of the semiconductor device. By the annealing step, it is possible to prevent a stress concentration phenomenon from occurring in a semiconductor substrate on which the field oxide film is formed, thereby reducing or eliminating a field oxide thinning phenomenon.
摘要翻译：一种用于形成高度集成的半导体器件的场氧化物膜的方法，其中在用于生长适于隔离半导体器件的元件的场氧化膜的场氧化膜形成步骤期间执行退火步骤。通过退火步骤，可以防止在其上形成场氧化膜的半导体衬底中发生应力集中现象，从而减少或消除场氧化物稀化现象。

38. 发明授权

US5985738A Method for forming field oxide of semiconductor device using wet and dry oxidation 失效
标题翻译：使用湿式和干式氧化形成半导体器件的场氧化物的方法
公开(公告)号：US5985738A
公开(公告)日：1999-11-16
申请号：US959205
申请日：1997-10-28
申请人： Se Aug Jang , Young Bog Kim , Moon Sig Joo , Byung Jin Cho , Jong Choul Kim
发明人： Se Aug Jang , Young Bog Kim , Moon Sig Joo , Byung Jin Cho , Jong Choul Kim
IPC分类号： H01L21/316 , H01L21/31 , H01L21/76 , H01L21/762
CPC分类号： H01L21/76202
摘要： A method for forming a field oxide of a semiconductor device is disclosed, which takes advantage of wet oxidation at an early stage of field oxidation to prevent the ungrowth of field oxide and dry oxidation at a later stage of field oxidation to make the slope of field oxide positive, thereby improving the production yield and the reliability of semiconductor device.
摘要翻译：公开了一种用于形成半导体器件的场氧化物的方法，其在场氧化的早期利用湿氧化，以防止在场氧化的后期阶段的场氧化物的不生长和干氧化以使场的斜率氧化物阳性，从而提高半导体器件的产量和可靠性。

39. 发明授权

US5841294A Method for measuring leakage current in junction region of semiconductor device 失效
标题翻译：测量半导体器件结区的漏电流的方法
公开(公告)号：US5841294A
公开(公告)日：1998-11-24
申请号：US672927
申请日：1996-06-28
申请人： Se Aug Jang , Tae Sik Song
发明人： Se Aug Jang , Tae Sik Song
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01R31/2608
摘要： A simple and accurate measurement of leakage current in the junction region of a semiconductor device involves a simple processing step carried out after element-isolating oxide films are formed. A method of measuring the junction leakage current involves providing a first-conduction-type silicon substrate, forming a first-conduction-type well in the substrate, forming element-isolating oxide films on the substrate, implanting second-conduction-type impurity ions in the substrate to form impurity diffusion regions, forming a conductive layer for an electrode over a resulting structure. Then, the method involves patterning the conductive layer to define plural dies that each have plural cells that each include the impurity diffusion regions and the conductive layer. Finally, reverse voltage is applied to the impurity diffusion regions and the substrate so as to measure the junction leakage current.
摘要翻译：在半导体器件的接合区域中的漏电流的简单且准确的测量包括在元件隔离氧化膜形成之后执行的简单的处理步骤。测量结漏电流的方法包括提供第一导电型硅衬底，在衬底中形成第一导电型阱，在衬底上形成元件隔离氧化膜，将第二导电型杂质离子注入所述衬底形成杂质扩散区域，在所得结构上形成用于电极的导电层。然后，该方法包括图案化导电层以限定多个管芯，每个管芯具有各自包含杂质扩散区域和导电层的多个单元。最后，向杂质扩散区域和衬底施加反向电压，以测量结漏电流。

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