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31. 发明申请

US20080246073A1 Nonvolatile Memory Devices Including a Resistor Region 审中-公开
标题翻译：包括电阻器区域的非易失性存储器件
公开(公告)号：US20080246073A1
公开(公告)日：2008-10-09
申请号：US12138712
申请日：2008-06-13
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

32. 发明申请

US20080079028A1 Semiconductor devices in which a cell gate pattern and a resistor pattern are formed of a same material and methods of forming the same 有权
标题翻译：其中单元栅极图案和电阻器图案由相同的材料形成的半导体器件及其形成方法
公开(公告)号：US20080079028A1
公开(公告)日：2008-04-03
申请号：US11648992
申请日：2007-01-03
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L27/10
CPC分类号： H01L27/0629 , H01L27/105 , H01L27/11526 , H01L27/11568 , H01L28/20
摘要： A semiconductor device is formed by providing a semiconductor substrate comprising a cell region, a peripheral circuit region, and a resistor region, forming a device isolation layer on the semiconductor substrate so as to define an active region, forming a first insulating layer and a polysilicon pattern on the active region of the peripheral circuit region, forming a second insulating layer, a charge storage layer, and a third insulating layer on the active region of the cell region, forming a conductive layer on the semiconductor substrate, and patterning the conductive layer to form conductive patterns on the third insulating layer of the cell region, the polysilicon pattern of the active region of peripheral circuit region, and the semiconductor substrate of the resistor region, respectively.
摘要翻译：通过提供包括单元区域，外围电路区域和电阻器区域的半导体衬底形成半导体器件，在半导体衬底上形成器件隔离层以限定有源区，形成第一绝缘层和多晶硅在外围电路区域的有源区上形成图案，在单元区域的有源区上形成第二绝缘层，电荷存储层和第三绝缘层，在半导体衬底上形成导电层，并且使导电层以在单元区域的第三绝缘层上形成导电图案，分别形成外围电路区域的有源区域的多晶硅图案和电阻器区域的半导体衬底。

33. 发明授权

US06828637B2 Semiconductor memory devices having dummy active regions 有权
标题翻译：半导体存储器件具有虚拟有源区
公开(公告)号：US06828637B2
公开(公告)日：2004-12-07
申请号：US10794533
申请日：2004-03-05
申请人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
发明人： Hong-Soo Kim , Jung-Dal Choi , Jong-Sun Sel , Yong-Joon Choi
IPC分类号： H01L2976
CPC分类号： H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having a dummy active region is provided, which includes a plurality of parallel main active regions and a dummy active region coupled to ends of the main active regions. The main preferably active regions are arranged in a main memory cell array region and extend to or through a dummy cell array region surrounding the main memory cell array region. Further, the dummy active region is perpendicular to the main active regions. A redundancy cell array region may intervene between the main memory cell array region and the dummy cell array region. In this case, the main active regions are extended to the dummy cell array region through the redundancy cell array region.
摘要翻译：提供了具有虚设有源区的半导体存储器件，其包括多个平行的主有效区和与主有效区的端部耦合的虚拟有源区。主要优选的有源区域被布置在主存储单元阵列区域中并且延伸到或通过围绕主存储单元阵列区域的虚设单元阵列区域。此外，虚拟有源区域垂直于主要有源区域。冗余单元阵列区域可以介于主存储单元阵列区域和虚设单元阵列区域之间。在这种情况下，主要有源区域通过冗余单元阵列区域扩展到虚拟单元阵列区域。

34. 发明授权

US08372711B2 Methods of fabricating semiconductor devices with sidewall conductive patterns 有权
标题翻译：制造具有侧壁导电图案的半导体器件的方法
公开(公告)号：US08372711B2
公开(公告)日：2013-02-12
申请号：US13110113
申请日：2011-05-18
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

35. 发明申请

US20120218816A1 Non-Volatile Memory Devices 有权
标题翻译：非易失性存储器件
公开(公告)号：US20120218816A1
公开(公告)日：2012-08-30
申请号：US13463060
申请日：2012-05-03
申请人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
发明人： Jong-Sun Sel , Jung-Dal Choi , Young-Woo Park , Jin-Taek Park
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/3427
摘要： A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a ground select line crossing the active region, and a string select line crossing the active region and spaced apart from the ground select line. A plurality of memory cell word lines may cross the active region between the ground select line and the string select line with about a same first spacing provided between adjacent ones of the plurality of word lines and between a last of the plurality of memory cell word lines and the string select line. A second spacing may be provided between the ground select line and a first of the plurality of memory cell word lines.
摘要翻译：非易失性存储器件可以包括半导体衬底，其包括其表面处的有源区，与有源区交叉的接地选择线，以及与有源区交叉并与地选线相隔的串选择线。多个存储单元字线可以与地线选择线和弦选择线之间的有源区域相交，并且与多个字线中的相邻字线之间以及多个存储单元字线中的最后一个之间提供大致相同的第一间隔和字符串选择行。可以在接地选择线和多个存储单元字线中的第一个之间提供第二间隔。

36. 发明授权

US07795643B2 Cell array of semiconductor memory device and a method of forming the same 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US07795643B2
公开(公告)日：2010-09-14
申请号：US11507511
申请日：2006-08-22
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： H01L29/94
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

37. 发明申请

US20100184263A1 METHODS OF FABRICATING FLASH MEMORY DEVICES HAVING SHARED SUB ACTIVE REGIONS 有权
标题翻译：制造具有共享子活动区域的闪存存储器件的方法
公开(公告)号：US20100184263A1
公开(公告)日：2010-07-22
申请号：US12725936
申请日：2010-03-17
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/8247
CPC分类号： H01L27/11524 , H01L27/115 , H01L27/11521 , Y10S257/905
摘要： Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
摘要翻译：闪存器件包括在衬底中的一对细长的，紧密间隔的主要有源区。亚基活性区域还设置在基底中，在一对细长的，紧密间隔开的主活性区域之间延伸。位线接触插头设置在子有源区上并且电接触，并且至少与次有源区一样宽。在远离副有源区域的位线接触插头上提供细长的位线并且电接触。

38. 发明授权

US07605473B2 Nonvolatile memory devices 失效
标题翻译：非易失性存储器件
公开(公告)号：US07605473B2
公开(公告)日：2009-10-20
申请号：US11403964
申请日：2006-04-13
申请人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
发明人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531
摘要： Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.
摘要翻译：提供制造非易失性存储器件的方法。在基板上形成隔离层。衬底具有存储区和阱接触区，并且隔离层限定衬底的有源区。在有源区上形成栅极绝缘层。栅极绝缘层被图案化以在其中限定开口。开口暴露衬底的阱接触区域的至少一部分，并且充当用于隔离层的后续蚀刻期间产生的电荷的电荷路径。还提供了相关的存储器件。

39. 发明申请

US20060273457A1 Data line layout in semiconductor memory device and method of forming the same 有权
标题翻译：半导体存储器件中的数据线布局及其形成方法
公开(公告)号：US20060273457A1
公开(公告)日：2006-12-07
申请号：US11444355
申请日：2006-06-01
申请人： Jong-Sun Sel , Jung-Dal Choi
发明人： Jong-Sun Sel , Jung-Dal Choi
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/105 , H01L27/1052
摘要： In one aspect, a semiconductor device is provided which includes a data block including M parallel and sequentially arranged data lines numbered {0, 1, 2, . . . n, n+1, . . . , m−1, m}, where M, n and m are positive integers, and where n
摘要翻译：在一个方面，提供了一种半导体器件，其包括数据块，该数据块包括M个并行且顺序排列的数字线，编号为{0,1,2。。。 n，n + 1，。。。，m-1，m}，其中M，n和m是正整数，并且其中n

40. 发明申请

US20060239077A1 NAND Flash Memory Device Having Dummy Memory cells and Methods of Operating Same 有权
标题翻译：具有虚拟存储器单元的NAND闪存器件和操作方法相同
公开(公告)号：US20060239077A1
公开(公告)日：2006-10-26
申请号：US11279607
申请日：2006-04-13
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

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