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1. 发明授权

US07795643B2 Cell array of semiconductor memory device and a method of forming the same 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US07795643B2
公开(公告)日：2010-09-14
申请号：US11507511
申请日：2006-08-22
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： H01L29/94
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

2. 发明申请

US20070104011A1 Cell array of semiconductor memory device and a method of forming the same 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US20070104011A1
公开(公告)日：2007-05-10
申请号：US11507511
申请日：2006-08-22
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

3. 发明授权

US08237199B2 Cell array of semiconductor memory device and a method of forming the same 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US08237199B2
公开(公告)日：2012-08-07
申请号：US12850677
申请日：2010-08-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： H01L29/94
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

4. 发明申请

US20100317157A1 CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FORMING THE SAME 有权
标题翻译：半导体存储器件的单元阵列及其形成方法
公开(公告)号：US20100317157A1
公开(公告)日：2010-12-16
申请号：US12850677
申请日：2010-08-05
申请人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
发明人： Jong-Sun Sel , Jung-Dal Choi , Chang-Seok Kang , Chang-Hyun Lee , Jang-Sik Lee , Vie-Na Kim
IPC分类号： H01L21/8239
CPC分类号： G11C8/14 , G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.
摘要翻译：电池阵列包括半导体衬底，其包括包括第一区域，第二区域和过渡区域的有源区域，第二区域与第一区域分离过渡区域，其中第二区域的顶表面处于与第一区域的顶表面不同的水平。单元阵列还包括跨越第一区域的多个字线。单元阵列还包括在有源区上交叉的选择线，其中选择线的至少一部分位于过渡区上方。

5. 发明授权

US07605430B2 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
标题翻译：具有鳍状有源区的非易失性存储器件及其制造方法
公开(公告)号：US07605430B2
公开(公告)日：2009-10-20
申请号：US11474699
申请日：2006-06-23
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

6. 发明申请

US20060289944A1 Nonvolatile memory devices having a fin shaped active region and methods of fabricating the same 失效
公开(公告)号：US20060289944A1
公开(公告)日：2006-12-28
申请号：US11474699
申请日：2006-06-23
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.

7. 发明授权

US07863686B2 Nonvolatile memory devices having a fin shaped active region 失效
标题翻译：具有鳍形有源区域的非易失性存储器件
公开(公告)号：US07863686B2
公开(公告)日：2011-01-04
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/66
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

8. 发明申请

US20090294837A1 Nonvolatile Memory Devices Having a Fin Shaped Active Region 失效
标题翻译：具有鳍形活动区域的非易失性存储器件
公开(公告)号：US20090294837A1
公开(公告)日：2009-12-03
申请号：US12536740
申请日：2009-08-06
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/792 , H01L29/78
CPC分类号： H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor substrate and a device isolation layer on the semiconductor substrate. A fin-shaped active region is formed between portions of the device isolation layer. A sidewall protection layer is formed on the sidewall of the fin-shaped active region where source and drain regions are formed. Thus, it may be possible to reduce the likelihood of an undesirable connection between an interconnection layer connected to the source and drain regions and a lower sidewall of the active region so that charge leakage from the interconnection layer to a substrate can be prevented or reduced. The sidewall protection layer may be formed using the device isolation layer. Alternatively, an insulating layer having an etch selectivity with respect to an interlayer insulating layer may be formed on the device isolation layer so as to cover the sidewall of the active region.
摘要翻译：非易失性存储器件包括半导体衬底和半导体衬底上的器件隔离层。翅片形有源区形成在器件隔离层的各部分之间。侧壁保护层形成在形成源区和漏区的鳍状有源区的侧壁上。因此，可以降低连接到源极和漏极区域的互连层和有源区域的下侧壁之间的不期望的连接的可能性，从而可以防止或减少从互连层到衬底的电荷泄漏。侧壁保护层可以使用器件隔离层形成。或者，可以在器件隔离层上形成具有相对于层间绝缘层的蚀刻选择性的绝缘层，以覆盖有源区的侧壁。

9. 发明申请

US20080246073A1 Nonvolatile Memory Devices Including a Resistor Region 审中-公开
标题翻译：包括电阻器区域的非易失性存储器件
公开(公告)号：US20080246073A1
公开(公告)日：2008-10-09
申请号：US12138712
申请日：2008-06-13
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L29/00
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。电池绝缘层形成在包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的半导体衬底的一部分上。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

10. 发明授权

US07399672B2 Methods of forming nonvolatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US07399672B2
公开(公告)日：2008-07-15
申请号：US11375983
申请日：2006-03-15
申请人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
发明人： Chang-Hyun Lee , Jung-Dal Choi , Chang-Seok Kang , Yoo-Cheol Shin , Jong-Sun Sel
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , B82Y10/00 , H01L21/823462 , H01L27/0629 , H01L27/11526 , H01L27/11546 , H01L27/11568
摘要： Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor.
摘要翻译：形成存储器件的方法包括在包括单元阵列区域和电阻器区域的半导体衬底中形成器件隔离层，器件隔离层延伸到电阻器区域中并在半导体衬底中限定有源区域。在电阻器区域中的器件隔离层上形成第一导电层。半导体衬底暴露在电池阵列区域中。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分上形成电池绝缘层。在半导体衬底的包括电阻器区域中的暴露的电池阵列区域，有源区域和器件隔离层的部分中的单元绝缘层上形成第二导电层。蚀刻第二导电层以在电池阵列区域中形成电池栅电极，并且同时从电阻器区域去除第二导电层，并且在电阻器区域中蚀刻第一导电层以形成电阻器。

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