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31. 发明授权

US08035098B1 Transistor with asymmetric silicon germanium source region 有权
标题翻译：晶体管与不对称硅锗源区
公开(公告)号：US08035098B1
公开(公告)日：2011-10-11
申请号：US11278618
申请日：2006-04-04
申请人： Jian Chen , James F. Buller , Akif Sultan
发明人： Jian Chen , James F. Buller , Akif Sultan
IPC分类号： H01L29/06 , H01L21/336
CPC分类号： H01L29/78618 , H01L29/665 , H01L29/66636 , H01L29/66659 , H01L29/66772 , H01L29/7848
摘要： The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
摘要翻译：本发明涉及具有不对称硅锗源区的晶体管及其制造方法。在一个说明性实施例中，晶体管包括形成在由硅构成的半导体衬底之上的栅电极，掺杂源区包括在半导体衬底中形成的锗掺杂的外延生长硅的区域和形成在半导体衬底中的掺杂漏极区基质。

32. 发明授权

US07989891B2 MOS structures with remote contacts and methods for fabricating the same 有权
标题翻译：具有远程触点的MOS结构及其制造方法
公开(公告)号：US07989891B2
公开(公告)日：2011-08-02
申请号：US11755930
申请日：2007-05-31
申请人： Jianhong Zhu , Jinrong Zhou , David Wu , James F. Buller
发明人： Jianhong Zhu , Jinrong Zhou , David Wu , James F. Buller
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L21/76895 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L27/1203 , H01L29/7843
摘要： MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.
摘要翻译：提供具有远程触点的MOS结构和用于制造这种MOS结构的方法。在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。第一和第二MOS晶体管形成在第一部分内部和第一部分内。晶体管基本上平行并且在它们之间限定了一个空间。沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

33. 发明授权

US07633103B2 Semiconductor device and methods for fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07633103B2
公开(公告)日：2009-12-15
申请号：US11846318
申请日：2007-08-28
申请人： Akif Sultan , James F. Buller , Kaveri Mathur
发明人： Akif Sultan , James F. Buller , Kaveri Mathur
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/7843
摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.
摘要翻译：提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层地区。有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。每个栅电极指部分的一部分覆盖有源区。圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

34. 发明申请

US20080303089A1 INTEGRATED CIRCUIT SYSTEM WITH TRIODE 有权
标题翻译：集成电路系统与TRIODE
公开(公告)号：US20080303089A1
公开(公告)日：2008-12-11
申请号：US11759454
申请日：2007-06-07
申请人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
发明人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/0617 , H01L27/0817 , H01L27/1203
摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.
摘要翻译：集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。

35. 发明申请

US20080085570A1 Distinguishing Between Dopant and Line Width Variation Components 有权
标题翻译：区分掺杂剂和线宽变化组分
公开(公告)号：US20080085570A1
公开(公告)日：2008-04-10
申请号：US11538872
申请日：2006-10-05
申请人： Akif Sultan , James F. Buller , David Donggang Wu
发明人： Akif Sultan , James F. Buller , David Donggang Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L22/14
摘要： A test structure includes first and second pluralities of transistors. The first plurality of transistors includes gate electrodes of a first length. The second plurality of transistors includes gate electrodes of a second length different than the first length. A channel area of the transistors in the first plurality is substantially equal to a channel area of the transistors in the second plurality. A method for using the test structure includes measuring a performance metric of the first and second pluralities of transistors. Variation in the performance metric associated with the first plurality of transistors is compared to variation in the performance metric associated with the second plurality of transistors to identify a random length variation component associated with the first plurality of transistors.
摘要翻译：测试结构包括第一和第二多个晶体管。第一多个晶体管包括第一长度的栅电极。第二多个晶体管包括与第一长度不同的第二长度的栅电极。第一多个晶体管的沟道面积基本上等于第二多个晶体管的沟道面积。使用测试结构的方法包括测量第一和第二多个晶体管的性能度量。将与第一多个晶体管相关联的性能度量的变化与与第二多个晶体管相关联的性能度量的变化进行比较，以识别与第一多个晶体管相关联的随机长度变化分量。

36. 发明授权

US5811334A Wafer cleaning procedure useful in the manufacture of a non-volatile memory device 失效
标题翻译：用于制造非易失性存储器件的晶片清洁程序
公开(公告)号：US5811334A
公开(公告)日：1998-09-22
申请号：US578178
申请日：1995-12-29
申请人： James F. Buller , Basab Bandyopadhyay , Shyam Garg , Nipendra J. Patel , Thomas E. Spikes, Jr.
发明人： James F. Buller , Basab Bandyopadhyay , Shyam Garg , Nipendra J. Patel , Thomas E. Spikes, Jr.
IPC分类号： H01L21/28 , H01L21/306 , H01L21/336 , H01L21/8247
CPC分类号： H01L21/02052 , H01L21/28167 , H01L29/66825 , Y10S438/906
摘要： A wafer surface cleaning method is provided comprising immersion of the wafer in a H.sub.2 O:NH.sub.4 OH:H.sub.2 O.sub.2 solution at a temperature less than 65.degree. C. prior to formation of a thin oxide such as a tunnel oxide or gate oxide. Immersion of the wafer in a sub-65.degree. C. NH.sub.4 OH results in a smoother wafer surface that increase the charge-to-breakdown (Q.sub.BD) of the subsequently formed oxide. In the tunnel oxide embodiment, the lower temperature solution also reduces the oxide etch rate of the solution enabling a minimum overgrowth of gate oxide which, in turn, enables the addition of an in situ growth temperature anneal of the gate oxide without altering other process parameters.
摘要翻译：提供了一种晶片表面清洁方法，其包括在形成诸如隧道氧化物或栅极氧化物的薄氧化物之前，将晶片浸入H 2 O:NH 4 OH:H 2 O 2溶液中，温度低于65℃。将晶片浸入低于65℃的NH 4 OH中导致更平滑的晶片表面，其增加随后形成的氧化物的电荷分解（QBD）。在隧道氧化物实施方案中，较低温度的溶液还降低了溶液的氧化物蚀刻速率，使得能够最小化栅极氧化物的过度生长，这进而使得能够添加栅极氧化物的原位生长温度退火而不改变其它工艺参数。

37. 发明授权

US5517047A Bonded wafer processing 失效
标题翻译：粘合晶片加工
公开(公告)号：US5517047A
公开(公告)日：1996-05-14
申请号：US287773
申请日：1994-08-09
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
摘要翻译：使用硅氧化粘合液的低温晶片接合允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液的成分。可以在粘合液中使用硝酸等氧化剂。当为氧化粘合提供额外的硅时，可以使用器件晶片和处理晶片上的介电层。由这种接合晶片制造的集成电路可能具有掩埋层和放射硬化，器件硅太厚以用于植入。

38. 发明授权

US08687417B2 Electronic device and method of biasing 有权
标题翻译：电子设备和偏置方法
公开(公告)号：US08687417B2
公开(公告)日：2014-04-01
申请号：US11867743
申请日：2007-10-05
申请人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Akif Sultan , Fred Hause , Donna Michael
发明人： Ruigang Li , Jingrong Zhou , David Donggang Wu , Zhonghai Shi , James F. Buller , Mark W. Michael , Akif Sultan , Fred Hause
IPC分类号： G11C11/34 , G11C16/04 , G11C16/02 , G11C16/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.
摘要翻译：第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。第一晶体管的电压阈值基于第一偏置电荷。第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。第二晶体管的电压阈值基于第二偏置电荷。

39. 发明申请

US20130105944A1 METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION 有权
标题翻译：金属电容器设计，改善可靠性和良好的电气连接
公开(公告)号：US20130105944A1
公开(公告)日：2013-05-02
申请号：US13716693
申请日：2012-12-17
申请人： Jianhong ZHU , James F. Buller
发明人： Jianhong ZHU , James F. Buller
IPC分类号： H01L49/02
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.
摘要翻译：形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段金属线，并且仅金属线的第一段与通孔重叠。该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

40. 发明申请

US20110108949A1 METAL CAPACITOR DESIGN FOR IMPROVED RELIABILITY AND GOOD ELECTRICAL CONNECTION 有权
标题翻译：金属电容器设计，改善可靠性和良好的电气连接
公开(公告)号：US20110108949A1
公开(公告)日：2011-05-12
申请号：US12615796
申请日：2009-11-10
申请人： Jianhong Zhu , James F. Buller
发明人： Jianhong Zhu , James F. Buller
IPC分类号： H01L27/08 , H01L21/4763
CPC分类号： H01L28/40 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A metal capacitor is formed with good conductivity for both nodes of the capacitor and improved reliability. An embodiment includes a first layer of alternating first and second metal lines, a second layer of alternating third and fourth metal lines, a dielectric layer between the first and second layers, and vias in the dielectric layer connecting the first and second metal lines with the third and fourth metal lines, respectively, wherein each metal line comprises alternating first segments having a first width and second segments having a second width, the first width being greater than the second width, each first segment lying adjacent to a second segment of an adjacent metal line, and only first segments of the metal lines overlapping the vias. The design enables the spacing between metal lines to be maintained, the spacing between via to metal to be increased, and via connection to be maintained for both nets, thereby improving the conductivity and reliability of the capacitor and maintaining capacitance density.
摘要翻译：形成对电容器的两个节点具有良好导电性的金属电容器，并提高可靠性。一个实施例包括交替的第一和第二金属线的第一层，交替的第三和第四金属线的第二层，第一和第二层之间的介电层，以及介电层中的通孔，将第一和第二金属线与第三和第四金属线，其中每个金属线包括具有第一宽度的交替的第一段和具有第二宽度的第二段，第一宽度大于第二宽度，每个第一段邻近相邻的第二段的第二段金属线，并且仅金属线的第一段与通孔重叠。该设计使得能够保持金属线之间的间距，通孔与金属之间的间隔增加，并且通过两个网络的连接来保持，从而提高电容器的导电性和可靠性并保持电容密度。

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