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1. 发明授权

US07989891B2 MOS structures with remote contacts and methods for fabricating the same 有权
标题翻译：具有远程触点的MOS结构及其制造方法
公开(公告)号：US07989891B2
公开(公告)日：2011-08-02
申请号：US11755930
申请日：2007-05-31
申请人： Jianhong Zhu , Jinrong Zhou , David Wu , James F. Buller
发明人： Jianhong Zhu , Jinrong Zhou , David Wu , James F. Buller
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L21/84 , H01L21/76895 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L27/1203 , H01L29/7843
摘要： MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.
摘要翻译：提供具有远程触点的MOS结构和用于制造这种MOS结构的方法。在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。第一和第二MOS晶体管形成在第一部分内部和第一部分内。晶体管基本上平行并且在它们之间限定了一个空间。沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

2. 发明授权

US08089125B2 Integrated circuit system with triode 有权
标题翻译：具有三极管的集成电路系统
公开(公告)号：US08089125B2
公开(公告)日：2012-01-03
申请号：US11759454
申请日：2007-06-07
申请人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
发明人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/0617 , H01L27/0817 , H01L27/1203
摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.
摘要翻译：集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。

3. 发明申请

US20080303089A1 INTEGRATED CIRCUIT SYSTEM WITH TRIODE 有权
标题翻译：集成电路系统与TRIODE
公开(公告)号：US20080303089A1
公开(公告)日：2008-12-11
申请号：US11759454
申请日：2007-06-07
申请人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
发明人： Jianhong Zhu , Ruigang Li , James F. Buller , David Wu
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/84 , H01L27/0617 , H01L27/0817 , H01L27/1203
摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.
摘要翻译：集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。

4. 发明授权

US06949436B2 Composite spacer liner for improved transistor performance 有权
标题翻译：用于提高晶体管性能的复合间隔衬
公开(公告)号：US06949436B2
公开(公告)日：2005-09-27
申请号：US10824428
申请日：2004-04-15
申请人： James F. Buller , David Wu , Scott Luning , Derick Wristers , Daniel Kadosh
发明人： James F. Buller , David Wu , Scott Luning , Derick Wristers , Daniel Kadosh
IPC分类号： H01L21/8238 , H01L21/336 , H01L27/092 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/6656 , H01L29/6659
摘要： Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.
摘要翻译：具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

5. 发明授权

US06727136B1 Formation of ultra-shallow depth source/drain extensions for MOS transistors 有权
标题翻译：形成MOS晶体管的超浅深度源极/漏极延伸
公开(公告)号：US06727136B1
公开(公告)日：2004-04-27
申请号：US10273291
申请日：2002-10-18
申请人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
发明人： James F. Buller , Derick J. Wristers , David Wu , Akif Sultan
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/823418 , H01L21/823814 , H01L29/1054 , H01L29/7833
摘要： A method of manufacturing a semiconductor device, comprising sequential steps of: (a) providing a semiconductor substrate including a pre-selected thickness strained lattice layer of a first semiconductor material at an upper surface thereof and an underlying layer of a second semiconductor material; and (b) introducing a dopant-containing species of one conductivity type into at least one pre-selected portion of the strained lattice layer of first semiconductor material to form a dopant-containing region therein with a junction at a depth substantially equal to the pre-selected thickness, wherein the second semiconductor material of the underlying layer inhibits diffusion thereinto of the dopant-containing species from the strained lattice layer, thereby controlling/limiting the depth of the junction to substantially the pre-selected thickness of the strained lattice layer.
摘要翻译：一种制造半导体器件的方法，包括以下顺序的步骤：（a）提供半导体衬底，该半导体衬底在其上表面包括预先选定的第一半导体材料的应变晶格层和第二半导体材料的下层; 和（b）将含有一种导电类型的含掺杂剂的物质引入到第一半导体材料的应变晶格层的至少一个预先选择的部分中，以在其中形成含有掺杂剂的区域，其中接合部的深度基本上等于预先 - 选择的厚度，其中下层的第二半导体材料抑制来自应变晶格层的含掺杂剂物质的扩散，从而将结的深度控制/限制到基本上预应变晶格层的预选厚度。

6. 发明授权

US07598161B2 Method of forming transistor devices with different threshold voltages using halo implant shadowing 有权
标题翻译：使用光晕植入物阴影形成具有不同阈值电压的晶体管器件的方法
公开(公告)号：US07598161B2
公开(公告)日：2009-10-06
申请号：US11861534
申请日：2007-09-26
申请人： Jingrong Zhou , Mark Michael , Donna Michael, legal representative , David Wu , James F. Buller , Akif Sultan
发明人： Jingrong Zhou , Mark Michael , David Wu , James F. Buller , Akif Sultan
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L29/1083
摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.
摘要翻译：本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

7. 发明授权

US07482252B1 Method for reducing floating body effects in SOI semiconductor device without degrading mobility 有权
标题翻译：降低SOI半导体器件中的浮体效应而不降低移动性的方法
公开(公告)号：US07482252B1
公开(公告)日：2009-01-27
申请号：US10740546
申请日：2003-12-22
申请人： David Wu , Qi Xiang , James F. Buller
发明人： David Wu , Qi Xiang , James F. Buller
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02694 , H01L21/02488 , H01L21/02532 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/7849
摘要： A method of forming a silicon-on-insulator semiconductor device including providing a substrate, forming an insulating layer on the substrate, forming a process layer on the insulating layer, implanting ions into the process layer adjacent the insulating layer, and forming a strained silicon layer over the process layer. Implanting ions into the process layer adjacent the insulating layer reduces floating body effects of the semiconductor device, while the strained silicon layer covers surface defects form by the implanted ions in the process layer to enhance mobility of the semiconductor device.
摘要翻译：一种形成绝缘体上半导体器件的方法，包括提供衬底，在衬底上形成绝缘层，在绝缘层上形成工艺层，将离子注入到与绝缘层相邻的处理层中，并形成应变硅层过程层。将离子注入到与绝缘层相邻的处理层中减少半导体器件的浮体效应，同时应变硅层通过处理层中的注入离子覆盖表面缺陷，以增强半导体器件的迁移率。

8. 发明授权

US08546855B2 Charging protection device 有权
标题翻译：充电保护装置
公开(公告)号：US08546855B2
公开(公告)日：2013-10-01
申请号：US13239865
申请日：2011-09-22
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

9. 发明申请

US20120007182A1 CHARGING PROTECTION DEVICE 有权
标题翻译：充电保护装置
公开(公告)号：US20120007182A1
公开(公告)日：2012-01-12
申请号：US13239865
申请日：2011-09-22
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L27/12
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

10. 发明授权

US08048753B2 Charging protection device 有权
标题翻译：充电保护装置
公开(公告)号：US08048753B2
公开(公告)日：2011-11-01
申请号：US12483737
申请日：2009-06-12
申请人： Jingrong Zhou , David Wu , James F. Buller
发明人： Jingrong Zhou , David Wu , James F. Buller
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L27/0255 , H01L21/84 , H01L27/1203
摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.
摘要翻译：形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径到SOI衬底的体硅层中的P +掺杂的衬底接触。

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