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31. 发明授权

US06621324B2 Redundant antifuse segments for improved programming efficiency 有权
标题翻译：冗余反熔丝段，以提高编程效率
公开(公告)号：US06621324B2
公开(公告)日：2003-09-16
申请号：US09683808
申请日：2002-02-19
申请人： John A. Fifield , William R. Tonti
发明人： John A. Fifield , William R. Tonti
IPC分类号： H01H3776
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure for improved programming efficiency is disclosed wherein the antifuse structure including a first node providing a first voltage, a plurality of antifuse elements, and a plurality of first switches. The plurality of antifuse elements are commonly connected to the first node. The plurality of first switches are sequentially activated during a program mode to individually apply the first voltage to each antifuse element. The antifuse structure may include a second node to which a second voltage is provided. Each of the plurality of first switches may be coupled between the second node and a corresponding one of the plurality of antifuse elements. The antifuse structure may also include a third node to which a fuse latch is connected. A plurality of second switches may be coupled between the third node and a corresponding one of the plurality antifuse elements. The plurality of second switches may be simultaneously activated during a read mode.
摘要翻译：公开了一种用于提高编程效率的反熔丝结构，其中反熔丝结构包括提供第一电压的第一节点，多个反熔丝元件和多个第一开关。多个反熔丝元件通常连接到第一节点。多个第一开关在编程模式期间被依次启动，以分别对每个反熔丝元件施加第一电压。反熔丝结构可以包括提供第二电压的第二节点。多个第一开关中的每一个可以耦合在第二节点和多个反熔丝元件中的对应的一个之间。反熔丝结构还可以包括连接熔丝闩锁的第三节点。多个第二开关可以耦合在第三节点和多个反熔丝元件中的对应的一个之间。多个第二开关可以在读取模式期间同时被激活。

32. 发明授权

US06177809B1 Redundant input/output driver circuit 失效
标题翻译：冗余输入/输出驱动电路
公开(公告)号：US06177809B1
公开(公告)日：2001-01-23
申请号：US09322470
申请日：1999-05-28
申请人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
发明人： William R. Tonti , Jack A. Mandelman , Anthony R. Bonaccio , Claude L. Bertin , Howard L. Kalter , John A. Fifield
IPC分类号： H03K19094
CPC分类号： H03K19/00384 , H03K19/0005
摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.
摘要翻译：由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态状态的第一个片外驱动电路。

33. 发明授权

US06177807B1 High frequency valid data strobe 失效
标题翻译：高频有效数据选通
公开(公告)号：US06177807B1
公开(公告)日：2001-01-23
申请号：US09322465
申请日：1999-05-28
申请人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
发明人： Claude L. Bertin , John A. Fifield , Erik L. Hedberg , Russell J. Houghton , William R. Tonti
IPC分类号： G03K1716
CPC分类号： G06F13/4086 , H03K5/06 , H04L25/0298
摘要： A processor with a memory send/received control circuit including a bus drive circuit and a detector circuit connected via control bus line to the control input of the memory. A data input line, or output line, or data input/output line is connected between the processor and the memory. A transmission line stub having a length that is incrementally variable is connected to the memory control input side of the control line 14. The impedance Z0 of the transmission line stub is equal to that of the control line and is open circuited at the end which results in voltage doubling to achieve high speed synchronization between control signals and data signals and to ensure valid data at high clock rates.
摘要翻译：具有存储器发送/接收控制电路的处理器，包括总线驱动电路和经由控制总线连接到存储器的控制输入端的检测器电路。数据输入线或输出线或数据输入/输出线连接在处理器和存储器之间。具有递增可变长度的传输线短截线连接到控制线14的存储器控制输入侧。传输线短截线的阻抗Z0等于控制线的阻抗Z0，并在结束时开路在电压倍增以实现控制信号和数据信号之间的高速同步，并确保在高时钟速率下的有效数据。

34. 发明授权

US5633605A Dynamic bus with singular central precharge 失效
标题翻译：具有单中心预充电的动态总线
公开(公告)号：US5633605A
公开(公告)日：1997-05-27
申请号：US450764
申请日：1995-05-24
申请人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
发明人： Jeffrey S. Zimmerman , John A. Fifield , Christopher P. Miller , Robert E. Busch
IPC分类号： G06F3/00 , G06F13/40 , H03K19/0185 , H03K19/0944 , H03K19/096
CPC分类号： G06F13/4077
摘要： A dynamic bus system with a central precharge device is disclosed that utilizes a controller circuit with a one-shot generator and write synchronizing circuits in combination with logic output modules having pull-up/down devices. The issuance of the output enable (OE) signals is interlocked with the turn-off of the precharge. Thus, data is written to the dynamic bus only when the precharge device is inactive, avoiding bus collisions. The resulting circuitry not only ensures the precharging of the bus before the data write to the bus, but will allow the synchronized OE signals to be issued during the same clock phase as the precharge signal.
摘要翻译：公开了一种具有中央预充电装置的动态总线系统，其利用具有单触发发生器的控制器电路和与具有上拉/下拉器件的逻辑输出模块相结合的写入同步电路。输出使能（OE）信号的发出与预充电的关断互锁。因此，仅当预充电设备处于非活动状态时才将数据写入动态总线，避免总线冲突。所产生的电路不仅可以确保在对总线的数据写入之前总线的预充电，而且允许在与预充电信号相同的时钟相位期间发出同步的OE信号。

35. 发明授权

US5561694A Self-timed driver circuit 失效
标题翻译：自定时驱动电路
公开(公告)号：US5561694A
公开(公告)日：1996-10-01
申请号：US506933
申请日：1995-07-26
申请人： John A. Fifield , Glenn P. Giacalone , Peter J. Jenkins
发明人： John A. Fifield , Glenn P. Giacalone , Peter J. Jenkins
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/01721 , H03K19/018521
摘要： A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.
摘要翻译：驱动器电路提供选择性地改变诸如预充电动态总线信号之类的输出信号的状态。电路检测数据是否与预充电总线信号相反，如果是，则将总线驱动到适当的状态。一旦数据有效就可以将数据驱动到总线上，即数据从电路的输入传播到总线，而不依赖于时钟或其他时序边沿，电路的输出是自定时的。

36. 发明授权

US5502940A Composite building element and methods of making and using the same 失效
标题翻译：复合建筑构件及其使用方法
公开(公告)号：US5502940A
公开(公告)日：1996-04-02
申请号：US108109
申请日：1993-08-17
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： B28B3/12 , B28B17/00 , B28B19/00 , E04D1/28 , E04D1/00
CPC分类号： E04D1/28 , B28B17/0018 , B28B19/00 , B28B3/123
摘要： A composite roofing element comprises a first layer of aggregate based material, a second layer of material having a density less than that of the first layer and has a wedge shaped region depending from its underside. The wedge shaped region is preferably integral with the second layer which can be made of an expanded polymer, expanded polystyrene being particularly suitable. Overlapping structure on the side edges and a recess in the thick end of the wedge enable adjacent elements to interlock with each other. By using such lightweight roofing elements the requirement for a substantial load bearing supporting structure is reduced.
摘要翻译：复合屋面元件包括第一层聚集体材料，第二层材料的密度小于第一层的密度，并且具有从其下侧垂下的楔形区域。楔形区域优选与可由膨胀聚合物制成的第二层成一体，发泡聚苯乙烯是特别合适的。侧边缘上的重叠结构和楔形物的厚端部中的凹部使相邻的元件彼此互锁。通过使用这种轻质的屋顶元件，减少了对承重支承结构的重要要求。

37. 发明授权

US5268028A Lightweight concrete roof tiles and similar products 失效
标题翻译：轻型混凝土屋顶瓦和类似产品
公开(公告)号：US5268028A
公开(公告)日：1993-12-07
申请号：US965989
申请日：1992-09-24
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： C04B28/04 , E04D1/16 , C04B24/34
CPC分类号： C04B28/04 , E04D1/16 , C04B2111/00594 , Y02W30/92
摘要： A lightweight concrete product in the form of a concrete roof tile is made from a cementitious mixture comprising a porous lightweight aggregate, an hydraulic cement, water, an agent for enhancing, flexural strength and an agent for enhancing the water retention capacity of the lightweight aggregate, the proportions being such that the product has satisfactory impact and flexural strengths.
摘要翻译： PCT No.PCT / GB88 / 00691 Sec。 371日期1989年6月19日 102（e）日期1989年6月19日PCT提交1988年8月22日PCT公布。出版物WO89 / 01918 日期为1989年3月9日。混凝土屋顶瓦形式的轻质混凝土产品由水泥混合物制成，该混凝土包含多孔轻质骨料，水硬性水泥，水，增强抗弯强度的试剂和用于增强轻质骨料的保水能力，使得产品具有令人满意的冲击力和弯曲强度。

38. 发明授权

US5260952A Fault tolerant logic system 失效
标题翻译：容错逻辑系统
公开(公告)号：US5260952A
公开(公告)日：1993-11-09
申请号：US693509
申请日：1991-04-30
申请人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
发明人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
IPC分类号： G01R31/317 , G06F11/08 , G06F11/10 , G06F11/16 , G11C29/00 , H03K19/00 , H03K19/003 , G01K31/28
CPC分类号： H03K19/00392 , G06F11/1044 , G11C29/84
摘要： A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.
摘要翻译：一种逻辑系统，包括用于提供第一差分输出的第一逻辑块; 第二逻辑块，与第一逻辑块相同，用于提供第二差分输出; 耦合到第一逻辑块的故障检测装置，用于检测第一差分输出中的故障; 以及耦合到第一和第二逻辑块和故障检测装置的选择装置，用于根据故障检测装置是否检测到故障来选择第一和第二逻辑块之一的输出。

39. 发明授权

US5228046A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5228046A
公开(公告)日：1993-07-13
申请号：US790797
申请日：1991-11-12
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级纠错能力，并且每个存储单元都与系统级错误校正功能相关联，通过提供用于禁用单位级错误校正的机制来增强存储器可靠性能力，例如，响应于在一个存储器单元中发生不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

40. 发明授权

US5058115A Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature 失效
标题翻译：故障容错计算机存储系统和组件采用双层错误校正和锁定功能检测
公开(公告)号：US5058115A
公开(公告)日：1991-10-15
申请号：US322255
申请日：1989-03-10
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

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