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    • 31. 发明申请
    • FIELD EFFECT TRANSISTOR
    • 场效应晶体管
    • US20080169472A1
    • 2008-07-17
    • US11623963
    • 2007-01-17
    • Andres BryantJia ChenEdward J. Nowak
    • Andres BryantJia ChenEdward J. Nowak
    • H01L29/786H01L29/04H01L21/336
    • H01L29/0665B82Y10/00H01L29/0673H01L29/42384H01L29/42392H01L29/78609H01L29/78696H01L51/0048H01L51/0508H01L51/055H01L51/102Y10S977/762
    • Disclosed are embodiments of a field effect transistor that incorporates an elongated semiconductor body with a spiral-shaped center channel region wrapped one or more times around a gate and with ends that extend outward from the center region in opposite directions away from the gate. Source/drain regions are formed in the end regions by either doping the end regions or by biasing a back gate to impart a preselected Fermi potential on the end regions. This disclosed structure allows the transistor size to be scaled without decreasing the effective channel length to the point where deleterious short-channel effects are exhibited. It further allows the transistor size to be scaled while also allowing the effective channel length to be selectively increased (e.g., by increasing the number of times the channel wraps around the gate). Also, disclosed are embodiments of an associated method of forming the transistor.
    • 公开了一种场效应晶体管的实施例,该场效应晶体管包括细长半导体本体,该半导体本体具有围绕栅极缠绕一次或多次的螺旋形中心沟道区域,并且具有从远离栅极的相反方向从中心区域向外延伸的端部。 通过掺杂末端区域或通过偏置后栅极在端部区域上形成源极/漏极区域,以在端部区域赋予预选的费米能电位。 该公开的结构允许晶体管尺寸被缩放而不会将有效沟道长度减小到显示有害的短沟道效应的程度。 它还允许对晶体管尺寸进行缩放,同时还允许有选择地增加有效沟道长度(例如,通过增加通道围绕栅极的次数)。 此外,公开了形成晶体管的相关方法的实施例。
    • 33. 发明申请
    • Shoe attachment assembly for various cycles
    • 鞋附件组件用于各种循环
    • US20070113428A1
    • 2007-05-24
    • US11653733
    • 2007-01-15
    • Guo JauJia Chen
    • Guo JauJia Chen
    • A43B5/00
    • A43B5/14
    • A shoe includes a shoe sole having one or more slots to detachably attach a cleat member which may be attached to cycle pedal. A plate is selectively attached to the shoe sole and has an opening to receive the cleat member, and to allow the cleat member to extend out of the plate, and to be attached to the cycle pedal. The plate includes one or more bulges or pegs to engage into the shoe sole and to anchor the plate to the shoe sole. One or more cleat elements may be detachably attached to the shoe sole, and partially received in depressions of the shoe sole, to anchor the cleat element to the shoe sole.
    • 鞋包括具有一个或多个狭槽的鞋底,以可拆卸地附接可附接到循环踏板的防滑钉构件。 板被选择性地附接到鞋底并具有用于接收防滑板构件的开口,并且允许防滑板构件延伸出板并且附接到循环踏板。 板包括一个或多个凸起或栓,以接合鞋底并将板锚定到鞋底上。 一个或多个防滑钉元件可以可拆卸地附接到鞋底,并且部分地容纳在鞋底的凹陷中,以将防滑钉元件锚定到鞋底。
    • 34. 发明申请
    • COMPLEMENTARY CARBON NANOTUBE TRIPLE GATE TECHNOLOGY
    • 补充碳纳米管三叶栅技术
    • US20070102747A1
    • 2007-05-10
    • US11164109
    • 2005-11-10
    • Jia ChenEdward Nowak
    • Jia ChenEdward Nowak
    • H01L29/76
    • H01L51/055B82Y10/00H01L27/283H01L51/0048H01L51/0558Y10S977/742Y10S977/94
    • Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.
    • 公开了克服CNTFET的固有双极性能的CNT技术。 本发明的一个实施例提供稳定的p型CNTFET或稳定的n型CNTFET。 本发明的另一实施例提供了一种互补的CNT器件。 为了克服CNTFET的双极性质,源极/漏极栅极被引入到与源极/漏极电极相对的CNT之下。 这些源极/漏极栅极用于向CNT的端部施加正或负电压,以将相应的FET分别构造为n型或p型CNTFET。 可以将两个相邻的CNTFET配置成互补CNT器件,其被配置为使得一个是n型CNTFET,另一个是p型CNTFET。 为了独立地调节各个CNTFET的阈值电压,也可以在CNT下面,特别是在与前栅极相对的CNT的沟道区下方引入背栅。 以这种方式,寄生电容和电阻最小化。
    • 36. 发明申请
    • Bandpass amplifier
    • 带通放大器
    • US20060001492A1
    • 2006-01-05
    • US10882215
    • 2004-07-02
    • Sheng ChangJia ChenCherng LiuHung ChenShu TangAlbert Chen
    • Sheng ChangJia ChenCherng LiuHung ChenShu TangAlbert Chen
    • H03F3/191
    • H03F3/191H03F2200/147H03F2200/222H03F2200/372
    • The present invention discloses a bandpass amplifier having gain and bandpass performance. The bandpass amplifier includes an input match unit for matching the gain of the amplifier and having a first filter response; a first bias unit electrically connected to the input match unit for driving the first terminal of the amplifier and having a first high pass filter response; a gain stage electrically connected to the first bias unit for providing the flat gain of the amplifier; a second bias unit electrically connected to the gain stage for driving the second terminal of the amplifier and having a second high pass filter response; and an output match unit electrically connected to the second bias unit for matching the gain of the amplifier and having a second filter response.
    • 本发明公开了具有增益和带通性能的带通放大器。 带通放大器包括用于匹配放大器的增益并具有第一滤波器响应的输入匹配单元; 电连接到输入匹配单元的第一偏置单元,用于驱动放大器的第一端并具有第一高通滤波器响应; 增益级,电连接到第一偏置单元,用于提供放大器的平坦增益; 电连接到增益级的第二偏置单元,用于驱动放大器的第二端并具有第二高通滤波器响应; 以及输出匹配单元,电连接到第二偏置单元,用于匹配放大器的增益并具有第二滤波器响应。
    • 40. 发明授权
    • Split poly-SiGe/poly-Si alloy gate stack
    • 分离多晶硅/多晶硅合金栅叠层
    • US07666775B2
    • 2010-02-23
    • US12104570
    • 2008-04-17
    • Kevin K. ChanJia ChenShih-Fen HuangEdward J. Nowak
    • Kevin K. ChanJia ChenShih-Fen HuangEdward J. Nowak
    • H01L21/3205
    • H01L21/2807H01L21/28052H01L21/28061H01L21/823835H01L21/823842H01L29/4916H01L29/4925H01L29/665
    • A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
    • 在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。 硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积(RTCVD)沉积高达至少70%的[Ge]的均匀且连续的多晶硅层。 在快速降低的温度下在氧环境中原位吹扫沉积室导致3至4厚度的薄SiO 2或SixGeyOz界面层。 薄的SiO 2或SixGeyOz界面层是足够薄且不连续的,以提供对栅极电流的很小的阻力,但是具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散,从而允许随后沉积的钴的硅化物。 栅电极堆叠结构用于nFET和pFET两者。