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1. 发明申请

US20060151844A1 Self-aligned process for nanotube/nanowire FETs 有权
公开(公告)号：US20060151844A1
公开(公告)日：2006-07-13
申请号：US11031168
申请日：2005-01-07
申请人： Phaedon Avouris , Roy Carruthers , Jia Chen , Christophe Detavernier , Christian Lavoie , Hon-Sum Wong
发明人： Phaedon Avouris , Roy Carruthers , Jia Chen , Christophe Detavernier , Christian Lavoie , Hon-Sum Wong
IPC分类号： H01L29/94 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

2. 发明申请

US20080026534A1 SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs 审中-公开
公开(公告)号：US20080026534A1
公开(公告)日：2008-01-31
申请号：US11866627
申请日：2007-10-03
申请人： Phaedon Avouris , Roy Carruthers , Jia Chen , Christophe Detavernier , Christian Lavoie , Hon-Sum Wong
发明人： Phaedon Avouris , Roy Carruthers , Jia Chen , Christophe Detavernier , Christian Lavoie , Hon-Sum Wong
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

3. 发明申请

US20070042586A1 STABILIZATION OF Ni MONOSILICIDE THIN FILMS IN CMOS DEVICES USING IMPLANTATION OF IONS BEFORE SILICIDATION 失效
标题翻译：使用硅氧烷之前的离子沉积的CMOS器件中的Ni单晶硅薄膜的稳定性
公开(公告)号：US20070042586A1
公开(公告)日：2007-02-22
申请号：US11551647
申请日：2006-10-20
申请人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
发明人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.
摘要翻译：在后续热处理中，形成稳定的金属硅化物膜例如接触（源极/漏极或栅极）的方法基本上不附着在本发明中，能够附着在Si- 在形成金属硅化物之前，将含硅层注入到含Si层中。植入的离子稳定膜，因为发现植入物基本上防止结块或至少延迟聚集到比没有使用植入物的情况下更高的温度。

4. 发明申请

US20050250301A1 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 有权
标题翻译：自对准金属与Ge形成的基板和由此形成的结构形成接触
公开(公告)号：US20050250301A1
公开(公告)日：2005-11-10
申请号：US10838378
申请日：2004-05-04
申请人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

5. 发明申请

US20050250319A1 Stabilization of Ni monosilicide thin films in CMOS devices using implantation of ions before silicidation 失效
标题翻译：在硅化物中使用离子注入，在CMOS器件中稳定Ni单硅化物薄膜
公开(公告)号：US20050250319A1
公开(公告)日：2005-11-10
申请号：US10838377
申请日：2004-05-04
申请人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
发明人： Roy Carruthers , Cedrik Coia , Christophe Detavernier , Christian Lavoie , Kenneth Rodbell
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming a stabilized metal silicide film, e.g., contact (source/drain or gate), that does not substantially agglomerate during subsequent thermal treatments, is provided. In the present invention, ions that are capable of attaching to defects within the Si-containing layer are implanted into the Si-containing layer prior to formation of metal silicide. The implanted ions stabilize the film, because the implants were found to substantially prevent agglomeration or at least delay agglomeration to much higher temperatures than in cases in which no implants were used.
摘要翻译：提供了一种用于形成稳定的金属硅化物膜的方法，例如接触（源极/漏极或栅极），其在随后的热处理期间基本上不附聚。在本发明中，在形成金属硅化物之前，将能够附着到含Si层内的缺陷的离子注入到含Si层中。植入的离子稳定膜，因为发现植入物基本上防止结块或至少延迟聚集到比没有使用植入物的情况下更高的温度。

6. 发明申请

US20050176247A1 Retarding agglomeration of Ni monosilicide using Ni alloys 有权
标题翻译：使用Ni合金抑制Ni一硅化物的团聚
公开(公告)号：US20050176247A1
公开(公告)日：2005-08-11
申请号：US11075289
申请日：2005-03-08
申请人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
发明人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
IPC分类号： C04B35/58 , C22F1/00 , C23C10/00 , H01L21/283 , H01L21/285 , H01L21/3205 , H01L21/44 , H01L21/60 , H01L21/768
CPC分类号： C04B35/58 , C04B35/58085 , C04B2235/40 , C04B2235/404 , C04B2235/405 , C04B2235/408 , C23C26/00 , C23C30/00 , H01L21/28518 , H01L21/76889
摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.
摘要翻译：一种用于提供半导体器件中有用的低电阻非聚集Ni单硅化物接触的方法。在制造基本上非团聚的Ni合金一硅化物的本发明方法中，包括以下步骤：在含Si衬底的一部分上形成金属合金层，其中所述金属合金层包括Ni和一种或多种合金添加剂），其中所述合金添加剂为Ti，V，Ge，Cr，Zr，Nb，Mo，Hf，Ta，W，Re，Rh，Pd或Pt或其混合物; 在将所述金属合金层的一部分转化为Ni合金一硅化物层的温度下退火金属合金层; 并除去未转化为Ni合金一硅化物的剩余金属合金层。选择合金添加剂用于相稳定性并阻止团聚。延迟聚集中最有效的合金添加剂在生产低薄层电阻的硅化物中是最有效的。

7. 发明申请

US20050059242A1 Reduction of silicide formation temperature on SiGe containing substrates 有权
标题翻译：在含SiGe的基板上降低硅化物的形成温度
公开(公告)号：US20050059242A1
公开(公告)日：2005-03-17
申请号：US10662900
申请日：2003-09-15
申请人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
发明人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , James Harper , Christian Lavoie
IPC分类号： H01L21/285 , H01L21/44 , H01L29/76
CPC分类号： H01L21/28518
摘要： A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.
摘要翻译：提供了一种解决在锗原子存在下形成二硅化钴期间显示的增加的成核温度的方法。硅化物形成温度的降低通过首先提供包括至少包含Ni的Co层作为添加元素在包含SiGe的衬底的顶部上的结构来实现。接下来，对该结构进行自对准硅化物工艺，其包括第一退火，选择性蚀刻步骤和第二退火，以在含SiGe的衬底上形成（Co，Ni）二硅化物的固溶体。至少包括Ni的Co层可以包括Co和Ni的合金层，Ni / Co的堆叠或Co / Ni的堆叠。还提供了包含（Co，Ni）二硅化物在含SiGe的衬底上的固溶体的半导体结构。

8. 发明申请

US20060160350A1 On-chip Cu interconnection using 1 to 5 nm thick metal cap 有权
标题翻译：使用1至5nm厚的金属帽的片上Cu互连
公开(公告)号：US20060160350A1
公开(公告)日：2006-07-20
申请号：US11037970
申请日：2005-01-18
申请人： John Bruley , Roy Carruthers , Lynne Gignac , Chao-Kun Hu , Eric Liniger , Sandra Malhotra , Stephen Rossnagel
发明人： John Bruley , Roy Carruthers , Lynne Gignac , Chao-Kun Hu , Eric Liniger , Sandra Malhotra , Stephen Rossnagel
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.
摘要翻译：公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

9. 发明申请

US20050250318A1 CVD tantalum compounds for FET gate electrodes 审中-公开
标题翻译：用于FET栅电极的CVD钽化合物
公开(公告)号：US20050250318A1
公开(公告)日：2005-11-10
申请号：US11180384
申请日：2005-07-13
申请人： Vijay Narayanan , Fenton McFeely , Keith Milkove , John Yurkas , Matthew Copel , Paul Jamison , Roy Carruthers , Cyril Cabral , Edmund Sikorskii , Elizabeth Duch , Alessandro Callegari , Sufi Zafar , Kazuhito Nakamura
发明人： Vijay Narayanan , Fenton McFeely , Keith Milkove , John Yurkas , Matthew Copel , Paul Jamison , Roy Carruthers , Cyril Cabral , Edmund Sikorskii , Elizabeth Duch , Alessandro Callegari , Sufi Zafar , Kazuhito Nakamura
IPC分类号： C23C16/34 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/49 , H01L29/772 , H01L29/78 , H01L21/3205 , H01L21/31 , H01L21/44 , H01L21/469 , H01L21/4763
CPC分类号： C23C16/34 , H01L21/28088 , H01L21/823828 , H01L29/4966 , H01L29/78
摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.
摘要翻译：公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。用TaN或TaSiN处理的器件显示出接近理想的特性。

10. 发明授权

US06391773B2 Method and materials for through-mask electroplating and selective base removal 失效
标题翻译：用于通孔电镀和选择性基底去除的方法和材料
公开(公告)号：US06391773B2
公开(公告)日：2002-05-21
申请号：US09733188
申请日：2000-12-09
申请人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
发明人： Panayotis Constantinou Andricacos , Cyril Cabral, Jr. , Roy Carruthers , Alfred Grill , Katherine Lynn Saenger
IPC分类号： H01L2144
CPC分类号： H01L28/60 , H01L21/2885 , H01L28/75
摘要： Multilayer metal materials are selected so that the materials will alloy or intermix under rapid thermal annealing conditions. The individual materials of the multilayers are preferably chosen such that at least one of the materials may be selectively etched with respect to the other material by wet chemical or electrochemical etching. For electroplating applications, the alloyed plating base material will assume some of the etch resistance of the original electrodeposit material such that a selective wet etch of the plating base can be performed without substantial undercutting. Furthermore, the graded composition alloy will exhibit other advantageous physical and chemical properties for electrode formation and use. The alloying or intermixing may be accomplished before or after patterning of the materials, for the instance wherein the materials deposited as blanket layers. Similarly, the alloying or intermixing may be accomplished before or after plating base removal for structures deposited by through-mask plating.
摘要翻译：选择多层金属材料，使得材料将在快速热退火条件下合金或混合。优选选择多层的单个材料，使得可以通过湿化学或电化学蚀刻相对于其它材料选择性地蚀刻至少一种材料。对于电镀应用，合金电镀基体材料将承受原始电沉积材料的一些耐蚀刻性，使得可以进行电镀基底的选择性湿法蚀刻而没有实质的底切。此外，分级组合物合金对于电极的形成和使用将表现出其它有利的物理和化学性质。合金化或混合可以在材料图案化之前或之后完成，例如其中作为覆盖层沉积的材料。类似地，合金化或混合可以在通过通过掩模电镀沉积的结构的电镀基底去除之前或之后完成。

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