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31. 发明授权

US5293384A Microprocessor bus interface protocol analyzer 失效
标题翻译：微处理器总线接口协议分析仪
公开(公告)号：US5293384A
公开(公告)日：1994-03-08
申请号：US771581
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay
发明人： James W. Keeley , Richard A. Lemay
IPC分类号： G06F13/42 , G06F11/00
CPC分类号： G06F13/4217
摘要： A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.
摘要翻译：高性能微处理器与其相关联，用于监视由微处理器发出的所有命令的协议监视装置，以及检测协议何时未正确完成或在某些预先建立的时间段内完成。当监视器/定时电路检测到协议错误时，监视装置操作以产生输出控制信号，该输出控制信号使微处理器能够继续进行进一步的处理。此外，监视装置包括用于存储微处理器在协议错误时执行的地址和命令的寄存器。相同的寄存器也用于捕获任何其他类型错误的地址和命令信息。

32. 发明授权

US4575792A Shared interface apparatus for testing the memory sections of a cache unit 失效
标题翻译：用于测试高速缓存单元的存储器部分的共享接口装置
公开(公告)号：US4575792A
公开(公告)日：1986-03-11
申请号：US364051
申请日：1982-03-31
申请人： James W. Keeley
发明人： James W. Keeley
IPC分类号： G06F12/00 , G11C29/14 , G11C29/48 , G06F11/00 , G06F13/00
CPC分类号： G11C29/14 , G11C29/48 , G06F12/00
摘要： The circuits of a cache unit constructed from a single board are divided into a cache memory section and a controller section. The cache unit is connectable to the central processing unit (CPU) of a data processing system through the interface circuits of the controller section. Test mode logic circuits included within the cache memory section enable cache memories to be tested without controller interference utilizing the same controller interface circuits.
摘要翻译：由单板构成的缓存单元的电路被分为高速缓冲存储器部分和控制器部分。高速缓存单元可通过控制器部分的接口电路连接到数据处理系统的中央处理单元（CPU）。包括在高速缓冲存储器部分内的测试模式逻辑电路使得能够使用相同的控制器接口电路来测试无需控制器干扰的高速缓存存储器。

33. 发明授权

US4464717A Multilevel cache system with graceful degradation capability 失效
标题翻译：多级缓存系统具有优雅的降级能力
公开(公告)号：US4464717A
公开(公告)日：1984-08-07
申请号：US364052
申请日：1982-03-31
申请人： James W. Keeley , Edwin P. Fisher , John L. Curley
发明人： James W. Keeley , Edwin P. Fisher , John L. Curley
IPC分类号： G06F12/08 , G06F12/12 , G11C29/00 , G06F13/00
CPC分类号： G11C29/88 , G06F12/126 , G06F2212/1032
摘要： The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.
摘要翻译：多级组关联高速缓存系统的目录和缓存存储器以存储器位置的级别组织。循环替换装置用于识别要更换哪一个多级别信息。该目录包括用于在高速缓冲存储器操作循环期间检测写入目录中的地址中的错误的奇偶校验检测装置。控制装置将这种奇偶校验错误与指示目录命中的信号组合以产生无效命中检测信号。响应于第一无效命中检测信号的发生，控制装置对循环装置以及高速缓存系统的其他部分进行调节，以将高速缓存操作限制在那些级别无错误的部分，从而正确地降低缓存操作。

34. 发明授权

US08379665B2 Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system 有权
标题翻译：用于光纤通道仲裁环路系统中多目标桥/路由器的接入公平性的装置和方法
公开(公告)号：US08379665B2
公开(公告)日：2013-02-19
申请号：US12475694
申请日：2009-06-01
申请人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
发明人： James W. Keeley , Douglas E. Sanders , Daniel W. Meyer , Andrew Hyonil Chong , Ju-Ching Tang
IPC分类号： H04J3/02
CPC分类号： H04L12/427
摘要： Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.
摘要翻译：装置和方法通过桥接装置改善了对光纤通道仲裁环（FC-AL）通信介质的公平访问。增强型桥接器件在当前打开的访问窗口中为通过桥接设备耦合到FC-AL通信介质的所有当前请求设备提供公平的访问。因此，当在开放访问窗口中存在同时请求时，环路上的所有设备无论是直接耦合还是通过桥接设备都可以确保公平地访问环路。

35. 发明授权

US5283870A Method and apparatus for avoiding processor deadly embrace in a multiprocessor system 失效
标题翻译：用于在多处理器系统中避免处理器致命包围的方法和装置
公开(公告)号：US5283870A
公开(公告)日：1994-02-01
申请号：US771296
申请日：1991-10-04
申请人： Thomas F. Joyce , James W. Keeley
发明人： Thomas F. Joyce , James W. Keeley
IPC分类号： G06F9/46 , G06F15/167 , G06F13/14
CPC分类号： G06F9/524 , G06F15/167
摘要： A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
摘要翻译：多处理器系统包括许多系统处理器，其紧密耦合到系统总线以共享主或系统存储器以及还紧密耦合到系统总线的多个板载存储器处理器。每个处理器都有一个高性能微处理器，通过微处理器的本地总线紧密耦合到板载或本地存储器。使用内存锁定协议访问系统内存，而本地内存可通过总线锁定协议访问。每个板上存储器处理器包括锁机构，其能够处理针对其本地存储器的存储器锁定命令，该存储器锁定命令经由系统总线从任何其他处理器接收并用于向系统存储器发出存储器锁定命令。

36. 发明授权

US4686621A Test apparatus for testing a multilevel cache system with graceful degradation capability 失效
标题翻译：用于测试具有优雅降级能力的多级缓存系统的测试装置
公开(公告)号：US4686621A
公开(公告)日：1987-08-11
申请号：US510079
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/20 , G06F11/267 , G06F12/08 , G11C29/00 , G06F11/00 , G11C7/00
CPC分类号： G06F12/126 , G06F12/0864 , G11C29/88 , G06F11/2236 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test apparatus coupled to the control apparatus and operates to selectively alter the operational states of the cache levels in response to commands received from a central processing unit for enabling testing of such control apparatus in addition to the other cache control areas.
摘要翻译：其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于从目录错误检查电路到被检测为没有错误的那些级别的错误信号选择性地降级缓存操作。测试装置耦合到控制装置并且操作以响应于从中央处理单元接收到的命令来选择性地改变高速缓存级别的操作状态，用于除了其他高速缓存控制区域之外还能够对这种控制装置进行测试。

37. 发明授权

US4562536A Directory test error mode control apparatus 失效
标题翻译：目录测试错误模式控制装置
公开(公告)号：US4562536A
公开(公告)日：1985-12-31
申请号：US509825
申请日：1983-06-30
申请人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
发明人： James W. Keeley , Robert V. Ledoux , Virendra S. Negi
IPC分类号： G06F11/00 , G06F11/10 , G06F11/267 , G06F12/08 , G06F12/12 , G11C29/00 , G11C29/02 , G06F13/00
CPC分类号： G06F11/1666 , G06F11/2215 , G06F12/0864 , G06F12/126 , G11C29/02 , G11C29/88 , G06F11/1064 , G06F11/20 , G06F2201/85 , G06F2212/1032
摘要： A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
摘要翻译：一个多级集合关联缓存系统，其目录和高速缓存存储组织到内存级别的位置。轮询更换装置用于识别要更换哪个级别的信息。该目录包括用于产生与地址一起写入目录位置的地址校验位的错误检查装置。响应于来自错误检查装置的错误信号的控制装置将高速缓存操作降级到被检测为没有错误的那些级别。耦合到替换和检查比特装置的测试错误模式控制装置使得地址校验位响应于从中央处理单元接收到的命令被选择性地强制为不正确的值，从而能够对来自其他的干扰的校验和控制装置进行验证由中央处理单元发起的操作。

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