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31. 发明授权

US07474638B2 Method and system for distributed baseband measurements 有权
标题翻译：分布式基带测量方法和系统
公开(公告)号：US07474638B2
公开(公告)日：2009-01-06
申请号：US10737432
申请日：2003-12-15
申请人： Yi He , Xiangzhou Joe Zhang , John E. Neeley
发明人： Yi He , Xiangzhou Joe Zhang , John E. Neeley
IPC分类号： H04Q7/00
CPC分类号： H04B17/327 , H04B2201/7071
摘要： A baseband measurement system includes a host and a Digital Immediate Frequency (DIF) subsystem. The DIF subsystem includes both hardware and software components, such as, for example, a microprocessor and its associated software, a FPGA, one or more ASICs, and memory. The baseband measurements are processed using the FPGA, ASICs, and the microprocessor and its software. The microprocessor controls the flow of the data in and out of the memory and distributes the processing tasks to both the hardware and software components in a cooperative manner. The microprocessor orchestrates the measurements and processing by operating as a measurement state machine. Selection of the proper component is based on the type of measurement and its processing requirements, as well as the current state of the hardware and software components. The host receives the processed data and performs post-processing operations if needed. The host also displays the processed data.
摘要翻译：基带测量系统包括主机和数字立即频率（DIF）子系统。 DIF子系统包括硬件和软件组件，例如微处理器及其相关软件，FPGA，一个或多个ASIC和存储器。基带测量使用FPGA，ASIC以及微处理器及其软件进行处理。微处理器控制数据进出存储器的流程，并以合作的方式将处理任务分配给硬件和软件组件。微处理器通过作为测量状态机进行操作来调节测量和处理。选择适当的组件是基于测量类型及其处理要求，以及硬件和软件组件的当前状态。主机接收处理后的数据，并根据需要执行后处理操作。主机还显示已处理的数据。

32. 发明申请

US20080270440A1 Data Compression for Producing Spectrum Traces 审中-公开
标题翻译：数据压缩生成光谱追踪
公开(公告)号：US20080270440A1
公开(公告)日：2008-10-30
申请号：US12092251
申请日：2006-11-01
申请人： Yi He , Kathryn A. Engholm
发明人： Yi He , Kathryn A. Engholm
IPC分类号： G06F17/30
CPC分类号： G10L19/0212 , G01R23/16
摘要： A data compression method for producing spectrum traces may divide signal data into multiple transform frames, produce a spectrum trace for each transform frame using a time domain to frequency domain transform, and combine the multiple frames from the analysis window into a single spectrum trace according to the spectrum amplitude of corresponding points in each frame. A device comprising a port to receive a signal or data set; and circuitry in communication with the port to segment the data record into frames, multiply each frame by a windowing function, transform each frame from a time domain representation to a frequency domain representation, and compress the frames using a detection function to create a single spectrum trace. This data compression provides flexibility to allow users to select analysis length, resolution bandwidth (RBW) and number of trace points independently, eliminating the coupling often found in traditional approaches.
摘要翻译：用于产生频谱轨迹的数据压缩方法可以将信号数据划分为多个变换帧，使用时域到频域变换产生每个变换帧的频谱轨迹，并根据分析窗口将多个帧从分析窗口组合成单个频谱轨迹每帧中对应点的频谱幅度。一种设备，包括用于接收信号或数据集的端口; 以及与端口通信的电路，用于将数据记录分割成帧，将每帧乘以加窗函数，将每个帧从时域表示转换为频域表示，并使用检测功能压缩帧以创建单个频谱跟踪。该数据压缩提供了灵活性，允许用户独立地选择分析长度，分辨率带宽（RBW）和跟踪点数量，消除了传统方法中常见的耦合。

33. 发明申请

US20080153274A1 Deep bitline implant to avoid program disturb 有权
标题翻译：深位线植入，以避免程序干扰
公开(公告)号：US20080153274A1
公开(公告)日：2008-06-26
申请号：US11646157
申请日：2006-12-26
申请人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
发明人： Timothy Thurgate , Yi He , Ming-Sang Kwan , Zhizheng Liu , Xuguang Wang
IPC分类号： H01L21/425 , G11C11/34
CPC分类号： H01L27/11568 , G11C5/02 , G11C5/06 , H01L27/115
摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.
摘要翻译：一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

34. 发明申请

US20080037330A1 RAMP GATE ERASE FOR DUAL BIT FLASH MEMORY 有权
标题翻译：用于双位闪存存储器的RAMP GATE擦除
公开(公告)号：US20080037330A1
公开(公告)日：2008-02-14
申请号：US11497597
申请日：2006-08-02
申请人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
发明人： Sheung-Hee Park , Gwyn Jones , Wing Leung , Edward Franklin Runnion , Ming-Sang Kwan , Xuguang Wang , Yi He
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/344 , G11C16/0475 , G11C16/0491 , G11C16/16 , G11C16/3445
摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.
摘要翻译：一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

35. 发明申请

US20070029604A1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
标题翻译：使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻
公开(公告)号：US20070029604A1
公开(公告)日：2007-02-08
申请号：US11546688
申请日：2006-10-12
申请人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
发明人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

36. 发明授权

US07058540B2 Method and system for accelerating power complementary cumulative distribution function measurements 失效
标题翻译：加速功率互补累积分布函数测量的方法和系统
公开(公告)号：US07058540B2
公开(公告)日：2006-06-06
申请号：US10737050
申请日：2003-12-15
申请人： Yi He , Gerald J. Ringel , Howard E. Hilton , Brian Barton
发明人： Yi He , Gerald J. Ringel , Howard E. Hilton , Brian Barton
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F17/18 , G01R21/133
摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.
摘要翻译：表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。直方图中每个直方图单元格的计数都存储在存储器中。每个浮点数作为存储器中对应的直方图bin的地址。然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并且从直方图数据导出CCDF曲线。将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

37. 发明授权

US06967873B2 Memory device and method using positive gate stress to recover overerased cell 有权
公开(公告)号：US06967873B2
公开(公告)日：2005-11-22
申请号：US10677790
申请日：2003-10-02
申请人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene G. Hamilton , Zhizheng Liu , Mark W. Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

38. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

39. 发明申请

US20050143982A1 Method and system for accelerating power complementary cumulative distribution function measurements 失效
标题翻译：加速功率互补累积分布函数测量的方法和系统
公开(公告)号：US20050143982A1
公开(公告)日：2005-06-30
申请号：US10737050
申请日：2003-12-15
申请人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
发明人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
IPC分类号： G06F15/00 , G06F17/18
CPC分类号： G06F17/18 , G01R21/133
摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.
摘要翻译：表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。直方图中每个直方图单元格的计数都存储在存储器中。每个浮点数作为存储器中对应的直方图bin的地址。然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并从直方图数据中导出CCDF曲线。将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

40. 发明授权

US06795342B1 System for programming a non-volatile memory cell 有权
标题翻译：用于编程非易失性存储单元的系统
公开(公告)号：US06795342B1
公开(公告)日：2004-09-21
申请号：US10307667
申请日：2002-12-02
申请人： Yi He , Zhizheng Liu , Mark W. Randolph , Sameer S. Haddad
发明人： Yi He , Zhizheng Liu , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475 , G11C16/0491
摘要： A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.
摘要翻译：一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压，电阻器又连接到地电位器。负编程偏置也可以应用于衬底和未选择的字线。

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