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31. 发明授权

US09013918B2 Two-terminal memory cell and semiconductor memory device based on different states of stable current 有权
标题翻译：基于不同稳态电流的双端存储单元和半导体存储器件
公开(公告)号：US09013918B2
公开(公告)日：2015-04-21
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/39 , G11C17/06 , H01L27/102
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.
摘要翻译：双端存储单元包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来将第一数据状态存储在存储单元中。可以通过在第一P型半导体层和第二N型半导体层之间施加接近存储单元的反向击穿区域的反向偏压来将第二数据状态存储在存储单元中。以这种方式，存储单元可以有效地用于数据存储。

32. 发明授权

US08766371B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08766371B2
公开(公告)日：2014-07-01
申请号：US13256866
申请日：2011-02-25
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/70
CPC分类号： H01L29/4983 , H01L21/823807 , H01L21/823842 , H01L21/823864 , H01L29/66545 , H01L29/7845
摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.
摘要翻译：提供半导体结构及其制造方法。根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

33. 发明授权

US08637935B2 Semiconductor device including embedded isolation regions and method for forming the same 有权
标题翻译：包括嵌入式隔离区的半导体器件及其形成方法
公开(公告)号：US08637935B2
公开(公告)日：2014-01-28
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

34. 发明授权

US08624315B2 Field effect transistor having an asymmetric gate electrode 有权
标题翻译：具有不对称栅电极的场效应晶体管
公开(公告)号：US08624315B2
公开(公告)日：2014-01-07
申请号：US13344955
申请日：2012-01-06
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L29/788
CPC分类号： H01L29/42376 , H01L21/28105 , H01L21/28114 , H01L21/28132 , H01L29/4983 , H01L29/512 , H01L29/517 , H01L29/66484 , H01L29/665 , H01L29/66613 , H01L29/7831
摘要： The gate electrode of a metal oxide semiconductor field effect transistor (MOSFET) comprises a source side gate electrode and a drain side gate electrode that abut each other near the middle of the channel. In one embodiment, the source side gate electrode comprises a silicon oxide based gate dielectric and the drain side gate electrode comprises a high-k gate dielectric. The source side gate electrode provides high carrier mobility, while the drain side gate electrode provides good short channel effect and reduced gate leakage. In another embodiment, the source gate electrode and drain gate electrode comprises different high-k gate dielectric stacks and different gate conductor materials, wherein the source side gate electrode has a first work function a quarter band gap away from a band gap edge and the drain side gate electrode has a second work function near the band gap edge.
摘要翻译：金属氧化物半导体场效应晶体管（MOSFET）的栅极包括源极侧栅电极和漏极侧栅电极，在栅极中间附近彼此邻接。在一个实施例中，源极侧栅极包括基于氧化硅的栅极电介质，漏极侧栅极包括高k栅极电介质。源极栅电极提供高载流子迁移率，而漏极侧栅电极提供良好的短沟道效应和减小的栅极泄漏。在另一个实施例中，源极栅极和漏极栅电极包括不同的高k栅极电介质堆叠和不同的栅极导体材料，其中源极侧栅电极具有远离带隙边缘的四分之一带隙的第一功函数和漏极侧栅电极在带隙边缘附近具有第二功函数。

35. 发明申请

US20130341713A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130341713A1
公开(公告)日：2013-12-26
申请号：US13623567
申请日：2012-09-20
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835 , H01L29/7848
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，一种方法包括在衬底上形成第一屏蔽层。该方法还包括以第一屏蔽层为掩模形成应力的源区和漏区中的一个。该方法还包括在衬底上形成第二屏蔽层，并且以第二屏蔽层作为掩模形成源区和漏区中的另一个。该方法还包括去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。该方法还包括形成栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

36. 发明授权

US08481379B2 Method for manufacturing fin field-effect transistor 有权
标题翻译：散射场效应晶体管的制造方法
公开(公告)号：US08481379B2
公开(公告)日：2013-07-09
申请号：US13375976
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/66795
摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.
摘要翻译：本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率的设备，并提高设备的性能。

37. 发明申请

US20130153913A1 Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor 有权
标题翻译：晶体管，晶体管的制造方法以及包含晶体管的半导体器件
公开(公告)号：US20130153913A1
公开(公告)日：2013-06-20
申请号：US13698276
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/02 , H01L27/088
CPC分类号： H01L21/02107 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/088 , H01L27/1203
摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.
摘要翻译：在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

38. 发明申请

US20130069167A1 SRAM CELL AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： SRAM单元及其制造方法
公开(公告)号：US20130069167A1
公开(公告)日：2013-03-21
申请号：US13509912
申请日：2011-11-21
申请人： Huilong Zhu , Qingqing Liang
发明人： Huilong Zhu , Qingqing Liang
IPC分类号： H01L27/092 , H01L21/336
CPC分类号： H01L21/823431 , H01L27/1104
摘要： A SRAM cell and a method for manufacturing the same are disclosed. In one embodiment, the SRAM cell may comprise: a semiconductor layer; and a first Fin Field Effect Transistor (FinFET) and a second FinFET formed on the semiconductor layer, wherein the first FinFET comprises a first fin formed by patterning the semiconductor layer, the first fin having a first top surface and a first bottom surface, wherein the second FinFET comprises a second fin formed by patterning the semiconductor layer, the second fin having a second top surface and a second bottom surface, and wherein the first top surface is substantially flush with the second top surface, the first and second bottom surfaces abut against the semiconductor layer, and the height of the second fin is greater than the height of the first fin.
摘要翻译：公开了SRAM单元及其制造方法。在一个实施例中，SRAM单元可以包括：半导体层; 以及形成在所述半导体层上的第一Fin场效应晶体管（FinFET）和第二FinFET，其中所述第一FinFET包括通过对所述半导体层进行图案化而形成的第一鳍，所述第一鳍具有第一顶表面和第一底表面，其中第二FinFET包括通过图案化半导体层形成的第二鳍片，第二鳍片具有第二顶表面和第二底表面，并且其中第一顶表面基本上与第二顶表面齐平，第一和第二底表面邻接并且第二散热片的高度大于第一散热片的高度。

39. 发明申请

US20130009244A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130009244A1
公开(公告)日：2013-01-10
申请号：US13379444
申请日：2011-08-01
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/42384 , H01L29/78648
摘要： The present application discloses an MOSFET and a method for manufacturing the same. The MOSFET comprises: a semiconductor substrate; a first insulation buried layer disposed on the semiconductor substrate; a back gate formed in a first semiconductor layer which is disposed on the first insulation buried layer; a second insulation buried layer disposed on the first semiconductor layer; source/drain regions formed in a second semiconductor layer which is disposed on the second insulation buried layer; a gate disposed on the second semiconductor layer; and electric connections to the source/drain regions, the gate and the back gate, wherein the back gate comprises first back gate regions of a first conductivity type which are disposed under the source/drain regions and a second back gate region of a second conductivity type which is disposed under a channel region, the first back gate regions adjoins the second back gate region, the first conductivity type is opposite to the second conductivity type, and the electric connection to the back gate comprise a conductive via contacted with one of the first back gate regions. The MOSFET, of any conductivity type, can have adjustable threshold voltage and reduced leakage current via the back gate between the source/drain regions by using the back gate in the form of a PNP junction or an NPN junction.
摘要翻译：本申请公开了一种MOSFET及其制造方法。 MOSFET包括：半导体衬底; 设置在所述半导体基板上的第一绝缘埋层; 形成在第一绝缘掩埋层上的第一半导体层中形成的背栅; 设置在所述第一半导体层上的第二绝缘埋层; 源极/漏极区域，形成在第二绝缘掩埋层上的第二半导体层中; 设置在所述第二半导体层上的栅极; 以及与源极/漏极区域，栅极和背栅极的电连接，其中所述背栅极包括设置在所述源极/漏极区域下方的第一导电类型的第一后栅极区域和具有第二导电性的第二背栅极区域所述第一导电类型与所述第二导电类型相反，并且与所述第二导电类型的电连接包括与所述第二导电类型之一接触的导电通孔，第一个后门区域。任何导电类型的MOSFET可以通过使用PNP结或NPN结形式的背栅，通过源极/漏极区之间的背栅极具有可调节的阈值电压和减小的漏电流。

40. 发明申请

US20130001665A1 MOSFET AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译： MOSFET及其制造方法
公开(公告)号：US20130001665A1
公开(公告)日：2013-01-03
申请号：US13379433
申请日：2011-08-02
申请人： Huilong Zhu , Miao Xu , Qingqing Liang
发明人： Huilong Zhu , Miao Xu , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/2652 , H01L21/2658 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/78648
摘要： The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate.
摘要翻译：本公开公开了一种MOSFET及其制造方法，其中，所述MOSFET包括：SOI晶片，其包含半导体基板，埋入绝缘层和半导体层，所述埋入绝缘层设置在所述半导体基板上，半导体层设置在掩埋绝缘层上; 设置在半导体层上的栅极堆叠; 源极区域和漏极区域，嵌入在半导体层中并设置在栅极叠层的两侧; 以及嵌入所述半导体层并夹在所述源极区域和所述漏极区域之间的沟道区域，其中所述MOSFET还包括背栅极和反向掺杂区域，并且其中所述背栅极嵌入所述半导体衬底中，所述反掺杂区域设置在沟道区域下方并嵌入在后栅极中，并且背栅极具有与反相掺杂区域相反的掺杂型。 MOSFET可以通过改变背栅极的掺杂类型来调节阈值电压。

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