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1. 发明申请

US20120281468A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US20120281468A1
公开(公告)日：2012-11-08
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： The present disclosure provides a semiconductor device and a semiconductor memory device. The semiconductor device can be used as a memory cell, and may comprise a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the semiconductor device by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the semiconductor device by applying a reverse bias, which is approaching to the reverse breakdown region of the semiconductor device, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the semiconductor device may be effectively used for data storage. The semiconductor memory device comprises an array of memory cells consisted of the semiconductor devices.
摘要翻译：本公开提供了半导体器件和半导体存储器件。半导体器件可以用作存储单元，并且可以包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。第一数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来存储在半导体器件中。第二数据状态可以通过在第一P型半导体层和第二N型半导体层之间施加正在接近半导体器件的反向击穿区域的反向偏压来存储在半导体器件中。以这种方式，半导体器件可以有效地用于数据存储。半导体存储器件包括由半导体器件组成的存储器单元的阵列。

2. 发明授权

US09013918B2 Two-terminal memory cell and semiconductor memory device based on different states of stable current 有权
标题翻译：基于不同稳态电流的双端存储单元和半导体存储器件
公开(公告)号：US09013918B2
公开(公告)日：2015-04-21
申请号：US13320331
申请日：2011-08-10
申请人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Xiaodong Tong , Huicai Zhong , Huilong Zhu
IPC分类号： G11C11/39 , G11C17/06 , H01L27/102
CPC分类号： G11C11/39 , G11C17/06 , G11C2213/72 , G11C2213/74 , H01L27/1027
摘要： A two-terminal memory cell includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, and a second N-type semiconductor layer arranged in sequence. A first data state may be stored in the memory cell by applying a forward bias, which is larger than a punch-through voltage VBO, between the first P-type semiconductor layer and the second N-type semiconductor layer. A second data state may be stored in the memory cell by applying a reverse bias, which is approaching to the reverse breakdown region of the memory cell, between the first P-type semiconductor layer and the second N-type semiconductor layer. In this way, the memory cell may be effectively used for data storage.
摘要翻译：双端存储单元包括依次布置的第一P型半导体层，第一N型半导体层，第二P型半导体层和第二N型半导体层。可以通过在第一P型半导体层和第二N型半导体层之间施加大于穿通电压VBO的正向偏压来将第一数据状态存储在存储单元中。可以通过在第一P型半导体层和第二N型半导体层之间施加接近存储单元的反向击穿区域的反向偏压来将第二数据状态存储在存储单元中。以这种方式，存储单元可以有效地用于数据存储。

3. 发明授权

US09312361B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09312361B2
公开(公告)日：2016-04-12
申请号：US13578872
申请日：2012-05-18
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: forming a first shielding layer on a substrate, and forming a first spacer on a sidewall of the first shielding layer; forming one of source and drain regions with the first shielding layer and the first spacer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming the other of the source and drain regions with the second shielding layer and the first spacer as a mask; removing at least a portion of the first spacer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of the second shielding layer or on a sidewall of a remaining portion of the first spacer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上形成第一屏蔽层，并在第一屏蔽层的侧壁上形成第一间隔物; 用第一屏蔽层和第一间隔件作为掩模形成源区和漏区之一; 在所述基板上形成第二屏蔽层，并移除所述第一屏蔽层; 用第二屏蔽层和第一间隔物作为掩模形成源区和漏区中的另一个; 去除所述第一间隔物的至少一部分; 以及形成栅极电介质层，以及在所述第二屏蔽层的侧壁或所述第一间隔物的剩余部分的侧壁上形成间隔物形式的栅极导体。

4. 发明授权

US09147745B2 Semiconductor devices formed using a sacrificial layer and methods for manufacturing the same 有权
标题翻译：使用牺牲层形成的半导体器件及其制造方法
公开(公告)号：US09147745B2
公开(公告)日：2015-09-29
申请号：US13981808
申请日：2012-07-24
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
IPC分类号： H01L29/66 , H01L29/78 , H01L29/786 , H01L21/28 , H01L29/51
CPC分类号： H01L29/66477 , H01L21/2815 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78639 , H01L29/78654
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。

5. 发明授权

US09064954B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09064954B2
公开(公告)日：2015-06-23
申请号：US13623567
申请日：2012-09-20
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7816 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835 , H01L29/7848
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，一种方法包括在衬底上形成第一屏蔽层。该方法还包括以第一屏蔽层为掩模形成应力的源区和漏区中的一个。该方法还包括在衬底上形成第二屏蔽层，并且以第二屏蔽层作为掩模形成源区和漏区中的另一个。该方法还包括去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。该方法还包括形成栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

6. 发明授权

US08637935B2 Semiconductor device including embedded isolation regions and method for forming the same 有权
标题翻译：包括嵌入式隔离区的半导体器件及其形成方法
公开(公告)号：US08637935B2
公开(公告)日：2014-01-28
申请号：US13266555
申请日：2011-04-19
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Huilong Zhu
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/78 , H01L29/7848
摘要： A method for forming a semiconductor device comprises: forming at least one gate stack structure and an interlayer material layer between the gate stack structures on a semiconductor substrate; defining isolation regions and removing a portion of the interlayer material layer and a portion of the semiconductor substrate which has a certain height in the regions, so as to form trenches; removing portions of the semiconductor substrate which carry the gate stack structures, in the regions; and filling the trenches with an insulating material. A semiconductor device is also provided. The area of the isolation regions may be reduced.
摘要翻译：一种用于形成半导体器件的方法包括：在半导体衬底上的栅堆叠结构之间形成至少一个栅叠层结构和层间材料层; 限定隔离区域并去除在该区域中具有一定高度的层间材料层和半导体衬底的一部分，以形成沟槽; 在所述区域中移除携带所述栅堆叠结构的所述半导体衬底的部分; 并用绝缘材料填充沟槽。还提供了半导体器件。可以减小隔离区域的面积。

7. 发明申请

US20130341713A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130341713A1
公开(公告)日：2013-12-26
申请号：US13623567
申请日：2012-09-20
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/66659 , H01L29/7834 , H01L29/7835 , H01L29/7848
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，一种方法包括在衬底上形成第一屏蔽层。该方法还包括以第一屏蔽层为掩模形成应力的源区和漏区中的一个。该方法还包括在衬底上形成第二屏蔽层，并且以第二屏蔽层作为掩模形成源区和漏区中的另一个。该方法还包括去除位于源区和漏区另一个旁边的第二屏蔽层的一部分。该方法还包括形成栅极电介质层，并在第二屏蔽层的剩余部分的侧壁上形成作为间隔物的栅极导体。

8. 发明授权

US08481379B2 Method for manufacturing fin field-effect transistor 有权
标题翻译：散射场效应晶体管的制造方法
公开(公告)号：US08481379B2
公开(公告)日：2013-07-09
申请号：US13375976
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/338
CPC分类号： H01L29/66545 , H01L29/66795
摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.
摘要翻译：本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率的设备，并提高设备的性能。

9. 发明申请

US20130153913A1 Transistor, Method for Fabricating the Transistor, and Semiconductor Device Comprising the Transistor 有权
标题翻译：晶体管，晶体管的制造方法以及包含晶体管的半导体器件
公开(公告)号：US20130153913A1
公开(公告)日：2013-06-20
申请号：US13698276
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/02 , H01L27/088
CPC分类号： H01L21/02107 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/088 , H01L27/1203
摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.
摘要翻译：在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

10. 发明申请

US20120309139A1 METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR 有权
标题翻译： FIN场效应晶体管的制造方法
公开(公告)号：US20120309139A1
公开(公告)日：2012-12-06
申请号：US13375976
申请日：2011-08-10
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795
摘要： An embodiment of the present invention discloses a method for manufacturing a FinFET, when a fin is formed, a dummy gate across the fin is formed on the fin, a source/drain opening is formed in both the cover layer and the first dielectric layer at both sides of the dummy gate, the source/drain opening is at both sides of the fin covered by the dummy gate and is an opening region surrounded by the cover layer and the first dielectric layer around it. In the formation of a source/drain region in the source/drain opening, stress is generated due to lattice mismatching, and applied to the channel due to the limitation by the source/drain opening in the first dielectric layer, thereby increasing the carrier mobility of the device, and improving the performance of the device.
摘要翻译：本发明的一个实施例公开了一种制造FinFET的方法，在翅片形成时，在翅片上形成跨鳍片的虚拟栅极，在覆盖层和第一电介质层中形成源极/漏极开口虚拟栅极的两侧，源极/漏极开口处于由虚拟栅极覆盖的鳍的两侧，并且是由覆盖层和围绕其的第一介电层包围的开口区域。在源极/漏极开口中的源极/漏极区域的形成中，由于晶格失配而产生应力，并且由于第一介电层中的源极/漏极开口的限制而施加到沟道，从而增加载流子迁移率的设备，并提高设备的性能。

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