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31. 发明申请

US20120153393A1 Transistor, Semiconductor Device Comprising the Transistor and Method for Manufacturing the Same 有权
标题翻译：晶体管，包括晶体管的半导体器件及其制造方法
公开(公告)号：US20120153393A1
公开(公告)日：2012-06-21
申请号：US13144906
申请日：2011-02-25
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78648 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L27/0605 , H01L27/1203 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.
摘要翻译：本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

32. 发明申请

US20150311319A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150311319A1
公开(公告)日：2015-10-29
申请号：US14406904
申请日：2012-08-17
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Chao Zhao , Tianchun Ye
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L29/785 , H01L29/7855
摘要： One embodiment of present invention provides a method for manufacturing a semiconductor structure, which comprises: forming a gate stack on a semiconductor substrate and removing parts of the substrates situated on two sides of the gate stack; forming sidewall spacers on sidewalls of the gate stack and on sidewalls of the part of the substrate under the gate stack; forming doped regions in parts of the substrate on two sides of the gate stack, and forming a first dielectric layer to cover the entire semiconductor structure; selectively removing parts of the gate stack and parts of the first dielectric layer to form a channel region opening and source/drain region openings; forming a high K dielectric layer on sidewalls of the channel region opening; and implementing epitaxy process to form a continuous fin structure that spans across the channel region opening and the source/drain region openings.
摘要翻译：本发明的一个实施例提供了一种用于制造半导体结构的方法，其包括：在半导体衬底上形成栅极叠层并去除位于栅极叠层两侧的衬底的部分; 在所述栅极堆叠的侧壁上以及在所述栅极堆叠下的所述衬底的所述部分的侧壁上形成侧壁间隔物; 在所述栅极堆叠的两侧上在所述衬底的部分中形成掺杂区域，以及形成覆盖整个半导体结构的第一介电层; 选择性地去除所述栅极堆叠的部分和所述第一介电层的部分以形成沟道区域开口和源极/漏极区域开口; 在沟道区域开口的侧壁上形成高K电介质层; 并且实现外延工艺以形成跨越沟道区域开口和源极/漏极区域开口的连续翅片结构。

33. 发明授权

US08895403B2 Transistor, method for fabricating the transistor, and semiconductor device comprising the transistor 有权
标题翻译：晶体管，晶体管的制造方法以及包括该晶体管的半导体器件
公开(公告)号：US08895403B2
公开(公告)日：2014-11-25
申请号：US13698276
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/00 , H01L21/02 , H01L27/088 , H01L21/8238 , H01L21/84 , H01L27/12
CPC分类号： H01L21/02107 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/088 , H01L27/1203
摘要： A transistor, a method for fabricating a transistor, and a semiconductor device comprising the transistor are disclosed in the present invention. The method for fabricating a transistor may comprise: providing a substrate and forming a first insulating layer on the substrate; defining a first device area on the first insulating layer; forming a spacer surrounding the first device area on the first insulating layer; defining a second device area on the first insulating layer, wherein the second device area is isolated from the first device area by the spacer; and forming transistor structures in the first and second device area, respectively. The method for fabricating a transistor of the present invention greatly reduces the space required for isolation, significantly decreases the process complexity, and greatly reduces fabricating cost.
摘要翻译：在本发明中公开了晶体管，晶体管的制造方法以及包括该晶体管的半导体器件。制造晶体管的方法可以包括：提供衬底并在衬底上形成第一绝缘层; 限定所述第一绝缘层上的第一器件区域; 在所述第一绝缘层上形成围绕所述第一器件区域的间隔物; 在所述第一绝缘层上限定第二器件区域，其中所述第二器件区域通过所述间隔物与所述第一器件区域隔离; 以及分别在第一和第二器件区域中形成晶体管结构。本发明的晶体管的制造方法大大降低了隔离所需的空间，显着地降低了工艺的复杂性，大大降低了制造成本。

34. 发明授权

US08846488B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08846488B2
公开(公告)日：2014-09-30
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L21/76 , H01L29/78 , H01L21/762 , H01L21/265
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

35. 发明申请

US20130221329A1 Graphene Device 审中-公开
标题翻译：石墨烯装置
公开(公告)号：US20130221329A1
公开(公告)日：2013-08-29
申请号：US13582431
申请日：2012-03-29
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Zhi Jin , Xinyu Liu , Tianchun Ye
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu , Zhi Jin , Xinyu Liu , Tianchun Ye
IPC分类号： H01L29/66
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/0665 , H01L29/1606 , H01L29/778
摘要： An embodiment of the invention discloses a graphene device comprising a plurality of graphene channels and a gate, wherein one end of all the graphene channels is connected to one terminal, all the graphene channels are in contact with and electrically connected with the gate, and the angles between the graphene channels and the gate are mutually different. Due to a different incident wave angle for a different graphene channel, each of the graphene channels has a different tunneling probability, each of the graphene channels has a different conduction condition, and the graphene device may be used as a device such as a multiplexer or a demultiplexer, etc.
摘要翻译：本发明的实施例公开了一种石墨烯装置，其包括多个石墨烯通道和一个浇口，其中所有石墨烯通道的一端连接到一个端子，所有的石墨烯通道与浇口接触并与门电连接，石墨烯通道和栅极之间的角度是相互不同的。由于不同石墨烯通道的不同的入射波角，每个石墨烯通道具有不同的隧道概率，每个石墨烯通道具有不同的导电条件，并且石墨烯装置可以用作诸如多路复用器或解复用器等

36. 发明授权

US08492210B2 Transistor, semiconductor device comprising the transistor and method for manufacturing the same 有权
标题翻译：晶体管，包括晶体管的半导体器件及其制造方法
公开(公告)号：US08492210B2
公开(公告)日：2013-07-23
申请号：US13144906
申请日：2011-02-25
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L21/84
CPC分类号： H01L29/78648 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L27/0605 , H01L27/1203 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.
摘要翻译：本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

37. 发明申请

US20130093041A1 Semiconductor Device and Method for Manufacturing the Same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130093041A1
公开(公告)日：2013-04-18
申请号：US13578598
申请日：2011-11-30
申请人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huaxiang Yin , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76224 , H01L21/26506 , H01L29/7842 , H01L29/7847
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: a substrate; a device region located on the substrate; and at least one stress introduction region separated from the device region by an isolation structure, with stress introduced into at least a portion of the at least one stress introduction region, wherein the stress introduced into the at least a portion of the at least one stress introduction region is produced by utilizing laser to illuminate an amorphized portion comprised in the at least one stress introduction region to recrystallize the amorphized portion. The semiconductor device according to an embodiment of the invention produces stress in a simpler manner and thereby improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：衬底; 位于所述基板上的器件区域; 以及至少一个应力引入区域，其通过隔离结构从所述器件区域分离，其中所述应力引入所述至少一个应力引入区域的至少一部分，其中所述应力引入所述至少一个应力的至少一部分引入区域通过利用激光照射包含在至少一个应力导入区域中的非晶化部分以使非晶化部分重结晶而产生。根据本发明的实施例的半导体器件以更简单的方式产生应力，从而提高器件的性能。

38. 发明申请

US20130049092A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130049092A1
公开(公告)日：2013-02-28
申请号：US13501518
申请日：2011-11-18
申请人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Miao Xu , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/4908 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： The present application discloses a semiconductor device comprising a source region and a drain region in an ultra-thin semiconductor layer; a channel region between the source region and the drain region in the ultra-thin semiconductor layer; a front gate stack above the channel region, the front gate comprising a front gate and a front gate dielectric between the front gate and the channel region; and a back gate stack below the channel region, the back gate stack comprising a back gate and a back gate dielectric between the back gate and the channel region, wherein the front gate is made of a high-Vt material, and the back gate is made of a low-Vt material. According to another embodiment, the front gate and the back gate are made of the same material, and the back gate is applied with a forward bias voltage during operation. The semiconductor device alleviates threshold voltage fluctuation due to varied thickness of the channel region by means of the back gate.
摘要翻译：本申请公开了一种包括超薄半导体层中的源极区域和漏极区域的半导体器件; 在超薄半导体层中的源极区域和漏极区域之间的沟道区域; 在所述沟道区域上方的前栅极堆叠，所述前栅极包括在所述前栅极和所述沟道区域之间的前栅极和前栅极电介质; 以及在沟道区域下方的背栅极堆叠，所述背栅叠层包括在所述背栅极和所述沟道区域之间的背栅极和背栅电介质，其中所述前栅极由高Vt材料制成，并且所述背栅极由低Vt材料制成。根据另一实施例，前栅极和后栅极由相同的材料制成，并且背栅在工作期间被施加正偏压。半导体器件通过后栅极减小由沟道区域的厚度变化引起的阈值电压波动。

39. 发明申请

US20130020578A1 Semiconductor Device and Method for Manufacturing the Same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20130020578A1
公开(公告)日：2013-01-24
申请号：US13521998
申请日：2011-11-30
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention may comprise: an active fin region which is arranged on an insulating layer; a threshold voltage adjusting layer arranged on top of the active fin region, which threshold voltage adjusting layer is used to adjust the threshold voltage of the semiconductor device; a gate stack which is arranged on the threshold voltage adjusting layer, on the sidewalls of the active fin region and on the insulating layer, and comprises a gate dielectric and a gate electrode formed on the gate dielectric; and a source region and a drain region formed in the active fin region on both sides of the gate stack respectively. The semiconductor device according to the invention comprises the threshold voltage adjusting layer which may adjust the threshold voltage of the semiconductor device. This provides a simple and convenient way capable of adjusting the threshold voltage of a semiconductor device comprising an active fin region.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明的实施例的半导体器件可以包括：布置在绝缘层上的有源鳍片区域; 设置在有源鳍片区域顶部的阈值电压调整层，该阈值电压调整层用于调整半导体器件的阈值电压; 栅极堆叠，其布置在阈值电压调节层上，在有源鳍片区域的侧壁和绝缘层上，并且包括形成在栅极电介质上的栅极电介质和栅电极; 以及分别形成在栅极堆叠两侧的有源鳍片区域中的源极区域和漏极区域。根据本发明的半导体器件包括可调节半导体器件的阈值电压的阈值电压调节层。这提供了能够调整包括有源鳍片区域的半导体器件的阈值电压的简单且方便的方式。

40. 发明申请

US20120319185A1 NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译： NAND结构及其制造方法
公开(公告)号：US20120319185A1
公开(公告)日：2012-12-20
申请号：US13063653
申请日：2010-06-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced.
摘要翻译：本发明提供了一种NAND门结构，包括：衬底; 形成在所述基板上的栅极绝缘层; 形成在所述基板中的源极/漏极区域; 形成在栅极绝缘体层上的中间栅极，在中间栅极的每一侧上的第一栅极和第二栅极，第一栅极和中间栅极之间以及第二栅极和中间栅极之间的第一侧壁间隔物，以及第二侧壁间隔物在第一栅极和第二栅极之外，其中，第一接触孔区域设置在中间栅极上，第二接触孔区域分别设置在第一栅极和第二栅极上，第一接触孔区域和第二接触孔地区交错排列。本发明提出了一种新的NAND结构及其制造方法。利用NAND结构，芯片面积的30-50％可以有效降低。

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