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31. 发明申请

US20120194792A1 METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY 有权
标题翻译：使用模拟或测量的地形来预测地震聚焦误差的方法和系统
公开(公告)号：US20120194792A1
公开(公告)日：2012-08-02
申请号：US13014803
申请日：2011-01-27
申请人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
发明人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
IPC分类号： G03B27/52
CPC分类号： G03F7/7065 , G03F7/70066 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F9/7026 , G06F17/5009 , G06F17/5081
摘要： A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
摘要翻译：公开了使用芯片形貌数据来预测光刻聚焦误差的方法和系统。可以测量或模拟地形数据的芯片地形数据。平面最适合地形数据，并计算残差。然后，残差用于对聚焦误差进行预测。金属与电介质的密度比也可用作确定预测的聚焦误差的因素。

32. 发明申请

US20090038960A1 APPARATUS AND METHOD OF ELECTROLYTIC REMOVAL OF METALS FROM A WAFER SURFACE 有权
标题翻译：从WAFER表面电解去除金属的装置和方法
公开(公告)号：US20090038960A1
公开(公告)日：2009-02-12
申请号：US11834971
申请日：2007-08-07
申请人： Hariklia Deligianni , Laertis Economikos , Catherine Ivers , Xiaoyan Shao
发明人： Hariklia Deligianni , Laertis Economikos , Catherine Ivers , Xiaoyan Shao
IPC分类号： C25F5/00 , B23H3/00 , C25F7/00
CPC分类号： B23H5/08
摘要： An apparatus and method designed to remove metals from a wafer surface using an electrolytic removal process. The apparatus includes a conductive pad having a plurality of alternating cathodes and anodes provided with a power source. The conductive pad is structured and configured to contact all metal islands on a surface of the wafer. Gaps are provided between pairs of the plurality of alternating cathodes and anodes.
摘要翻译：一种设计用于使用电解去除工艺从晶片表面去除金属的设备和方法。该装置包括具有多个具有电源的交替阴极和阳极的导电焊盘。导电焊盘被构造和配置成接触晶片表面上的所有金属岛。在多个交替阴极和阳极的成对之间提供间隙。

33. 发明授权

US07040966B2 Carbonation of pH controlled KOH solution for improved polishing of oxide films on semiconductor wafers 失效
标题翻译：碳酸化pH控制的KOH溶液，以改善对半导体晶片上的氧化膜的抛光
公开(公告)号：US07040966B2
公开(公告)日：2006-05-09
申请号：US10825849
申请日：2004-04-16
申请人： Joseph F. Salfelder , Wayne Swart , Gopalakrishna B. Prabhu , Srinivas R. Mirmira , Laertis Economikos , Fen Fen Jamin , Donald J. Delehanty , Daniel Heenan , Joseph M. Danza
发明人： Joseph F. Salfelder , Wayne Swart , Gopalakrishna B. Prabhu , Srinivas R. Mirmira , Laertis Economikos , Fen Fen Jamin , Donald J. Delehanty , Daniel Heenan , Joseph M. Danza
IPC分类号： B24B1/00
CPC分类号： H01L21/31053
摘要： A method and polishing system for planarizing a substrate having one or more materials formed thereon. The method generally includes positioning the substrate in proximity with a polishing pad, dispensing a polishing fluid to the polishing pad, the polishing fluid being subjected to carbonation prior to being dispensed to the polishing pad, and polishing the substrate. The polishing system generally includes a polishing platen having a polishing pad disposed thereon and in proximity to the substrate, a controller configured to cause the polishing pad to contact the substrate, and a polishing fluid delivery system to deliver a polishing fluid to the polishing pad, the polishing fluid delivery system including a carbonation system.
摘要翻译：一种用于平坦化其上形成有一种或多种材料的基板的方法和抛光系统。该方法通常包括将衬底定位在抛光垫附近，将抛光流体分配到抛光垫，抛光流体在分配到抛光垫之前进行碳酸化，并抛光衬底。抛光系统通常包括具有设置在其上并且靠近基板的抛光垫的抛光台板，配置成使抛光垫与基板接触的控制器和抛光流体输送系统以将抛光流体输送到抛光垫，抛光液输送系统包括碳酸化系统。

34. 发明授权

US06776885B2 Integrated plating and planarization apparatus having a variable-diameter counterelectrode 有权
标题翻译：具有可变直径对电极的集成电镀和平坦化装置
公开(公告)号：US06776885B2
公开(公告)日：2004-08-17
申请号：US10294199
申请日：2002-11-14
申请人： Laertis Economikos , Hariklia Deligianni , John M. Cotte , Panayotis C. Andricacos
发明人： Laertis Economikos , Hariklia Deligianni , John M. Cotte , Panayotis C. Andricacos
IPC分类号： C25D1400
CPC分类号： C25D5/48 , C25D17/00 , C25D17/001 , C25D17/10
摘要： An apparatus for plating and planarizing metal on a substrate includes a plurality of dispensing segments, each having at least one hole for dispensing electroplating solution onto the substrate. The dispensing segments form a circular counterelectrode and are movable with respect to each other during an electroplating process, so that the counterelectrode has a variable diameter. The electroplating solution is thus dispensed on an annular portion of the substrate having a diameter corresponding to the diameter of the counterelectrode; accordingly, the variable-diameter counterelectrode permits localized delivery of the plating solution to the substrate.
摘要翻译：用于在基底上电镀和平面化金属的装置包括多个分配段，每个分配段具有至少一个用于将电镀溶液分配到衬底上的孔。分配段形成圆形反电极并且可以在电镀过程期间相对于彼此移动，使得反电极具有可变的直径。因此，电镀溶液被分配在具有对应于反电极的直径的直径的基底的环形部分上; 因此，可变直径对电极允许将电镀液局部输送到基板。

35. 发明授权

US06448169B1 Apparatus and method for use in manufacturing semiconductor devices 失效
标题翻译：用于制造半导体器件的装置和方法
公开(公告)号：US06448169B1
公开(公告)日：2002-09-10
申请号：US08576185
申请日：1995-12-21
申请人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
发明人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
IPC分类号： H01L2144
CPC分类号： B23K3/0607 , B23K2101/40 , H05K3/3484 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/043 , Y10T29/49204
摘要： An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.
摘要翻译：一种用于制造半导体器件的装置包括具有多个IO引脚的输入输出（IO）面，并且位于与沉积器邻接的操作位置。该装置包括将第一保持构件保持在第一位置; 保持半导体器件处于操作位置的第二保持构件。存储器和半导体器件在操作位置协作以将焊球连接结构沉积到IO焊盘。该装置还包括用于将存储器和半导体器件中的至少一个从操作位置移动到临时取向的分离构件。临时方向建立了适于使焊球连接结构与沉积器脱离接触的存放器和半导体器件之间的间隔距离。

36. 发明授权

US06218236B1 Method of forming a buried bitline in a vertical DRAM device 失效
标题翻译：在垂直DRAM器件中形成掩埋位线的方法
公开(公告)号：US06218236B1
公开(公告)日：2001-04-17
申请号：US09238729
申请日：1999-01-28
申请人： Laertis Economikos , Hussein Ibrahim Hanafi , Thomas Safron Kanarsky , Cheruvu Suryanarayana Murthy
发明人： Laertis Economikos , Hussein Ibrahim Hanafi , Thomas Safron Kanarsky , Cheruvu Suryanarayana Murthy
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L27/10876 , H01L27/10888
摘要： A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.
摘要翻译：公开了一种在垂直半导体存储器件中形成浅扩散掩埋位线的方法，其利用退火和氧化来将掺杂剂原子引入并堆积到向外扩散区域中。在两个不同温度范围进行的退火/氧化允许在最大掺杂浓度下制造尽可能低的电阻，同时在垂直柱的表面界面附近形成掩埋位线。还公开了包含超扩散掩埋位线区域的半导体存储器件。

37. 发明授权

US06208008B1 Integrated circuits having reduced stress in metallization 失效
标题翻译：集成电路在金属化中具有降低的应力
公开(公告)号：US06208008B1
公开(公告)日：2001-03-27
申请号：US09260702
申请日：1999-03-02
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L2941
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译：通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角在施加外部（即钝化）层之前，例如，互连）。关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化或者沿着垂直侧壁的下部产生锥形间隔物。这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

38. 发明授权

US06198167B1 Semiconductor structure exhibiting reduced contact resistance and method for fabrication 有权
标题翻译：具有降低的接触电阻的半导体结构和制造方法
公开(公告)号：US06198167B1
公开(公告)日：2001-03-06
申请号：US09301567
申请日：1999-04-29
申请人： Laertis Economikos , Johnathan Faltermeier , Byeongju Park
发明人： Laertis Economikos , Johnathan Faltermeier , Byeongju Park
IPC分类号： H01L2348
CPC分类号： H01L29/66757 , H01L21/28525 , H01L21/28562 , H01L29/78621
摘要： A semiconductor structure of reduced contact resistance is provided by providing a layer of amorphous silicon-derived material on an epitaxial silicon substrate having an average dopant concentration of at least about 1020 atoms/cm3 in the contact material within about 500 Å of the substrate.
摘要翻译：通过在外延硅衬底上提供一层非晶硅衍生材料，该衬底的平均掺杂剂浓度为至少约1020原子/ cm3的接触材料，在衬底的大约500埃内提供。

39. 发明授权

US06180480B2 Germanium or silicon-germanium deep trench fill by melt-flow process 失效
标题翻译：锗或硅锗深沟通过熔体流动过程填充
公开(公告)号：US06180480B2
公开(公告)日：2001-01-30
申请号：US09162100
申请日：1998-09-28
申请人： Laertis Economikos , Byeongju Park
发明人： Laertis Economikos , Byeongju Park
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L27/1087 , H01L29/66181
摘要： A trench capacitor comprising a substrate, a trench formed in the substrate, and conductive doped germanium or silicon-germanium alloy fill material completely filling the trench. The process for creating the capacitor comprises depositing the conductive doped germanium or silicon-germanium alloy in the trench and in a fill layer over the substrate and annealing the wafer at a temperature at which the fill layer melts and completely flows into the trench but the wafer does not melt. The process further includes depositing a silicon cap layer on top of the fill layer to prevent oxidation of the fill layer. The trench may further include one or more of a buffer layer, a metal layer, and a thermal-stress-reduction layer between the trench walls and the fill material.
摘要翻译：包括衬底，形成在衬底中的沟槽和完全填充沟槽的导电掺杂锗或硅 - 锗合金填充材料的沟槽电容器。用于制造电容器的工艺包括将导电掺杂的锗或硅 - 锗合金沉积在衬底上的沟槽和填充层中，并在填充层熔融并完全流入沟槽但晶片的温度下退火晶片不融化该方法还包括在填充层的顶部上沉积硅帽层以防止填充层氧化。沟槽还可包括缓冲层，金属层和沟槽壁与填充材料之间的热应力减小层中的一个或多个。

40. 发明授权

US6149048A Apparatus and method for use in manufacturing semiconductor devices 失效
公开(公告)号：US6149048A
公开(公告)日：2000-11-21
申请号：US057421
申请日：1998-04-08
申请人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
发明人： William Brearley , Laertis Economikos , Paul F. Findeis , Kimberley A. Kelly , Bouwe W. Leenstra , Arthur Gilman Merryman , Eric Daniel Perfecto , Chandrika Prasad , James Patrick Wood , Roy Yu
IPC分类号： B23K3/06 , H05K3/34 , B23K1/00
CPC分类号： B23K3/0607 , H05K3/3484 , B23K2201/40 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/043 , Y10T29/49204
摘要： An apparatus for use in manufacturing a semiconductor device includes an input-output (IO) face having a plurality of IO lands, and is situated in an operating position in abutting relation with a depositor. The apparatus includes a first holding member holding the depositor in a first position; a second holding member holding the semiconductor device in the operating position. The depositor and the semiconductor device cooperate in the operating position to deposit solder ball connection structures to the IO lands. The apparatus further includes a separating member for moving at least one of the depositor and the semiconductor device from the operating position to an interim orientation. The interim orientation establishes a separation distance intermediate the depositor and the semiconductor device appropriate to disengage the solder ball connecting structures from the depositor.

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