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31. 发明专利

JP2000092703A INPUT/OUTPUT BUFFER CIRCUIT DEVICE 失效
公开(公告)号：JP2000092703A
公开(公告)日：2000-03-31
申请号：JP26270198
申请日：1998-09-17
申请人： HITACHI LTD
发明人： KAMINAGA YASUO , MORIOKA MICHIO , YAMADA TSUTOMU , KUROSAWA KENICHI
IPC分类号： H02J1/00
摘要： PROBLEM TO BE SOLVED: To prevent the deterioration and destruction of a group of LSIs in different kinds of power supply systems, by inputting one rank higher power supply voltages to voltage regulators, and by correcting the natural logarithmic discharging characteristic between each of the power supplies at the time of power interruption in response to each load condition of the power supplies. SOLUTION: Correcting capacity 71 is provided for correcting the natural logarithmic discharging characteristic at the time of power interruption. Also, this device is structured in such a way that power in inputted from power supply higher by one rank into each of voltage regulators 2, 3. Then, when power is impressed, each input voltage raises the output sides in sequence with the minimum drop voltage of the voltage regulators 2, 3 so that the power supply secures the electric potential of VCC1>VCC2>VCC3, a condition needed to be observed. On the other hand, when the power supply unit 1 is turned off, the addition of the correcting capacity 71 makes it possible to maintain VCC1>VCC2>VCC3, a condition needed to be observed at the time of power interruption. As a result, the deterioration and destruction of a group of LSIs can be prevented in different kinds of power supply systems.

32. 发明专利

JPH11341038A NODE DEVICE AND DATA COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH11341038A
公开(公告)日：1999-12-10
申请号：JP14681998
申请日：1998-05-28
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , TAKEWA HIDEHITO , OKURA TAKANORI , YAMADA TSUTOMU , OGURA MAKOTO , SAITO MASAHIKO , ARITA YUTAKA
IPC分类号： G06F15/16 , G06F15/163 , G06F15/177 , H04L12/44
摘要： PROBLEM TO BE SOLVED: To execute a program to be activated after memory transfer at high speed by allowing plural nodes to execute cyclically performing memory transfer by different time slots and allowing the respective nodes to activate the processing using data based on the cycle of mutual memory transfer completion among all the nodes. SOLUTION: Cables 3a to 3d are star type LANs, and each of nodes 1a to 1d performs memory transfer and multi-address communication therefor through each of the cables 3a to 3d. In order to avoid the time collision of data from each of the nodes 1a to 1d, each of the nodes 1a to 1d uses time slots of different times and performs data transmission. Each of the nodes 1a to 1d informs processors in each of data communication devices 2a to 2d of reception completion interruption at the timing at the time of data reception completion of all the other time slots other than its own. It is possible to inform completion of the memory transfer processing by interrupting the processor and the next control program and the next processing are executed at high speed.

33. 发明专利

JPH10116225A ADDRESS CONVERTING CIRCUIT AND MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JPH10116225A
公开(公告)日：1998-05-06
申请号：JP27056796
申请日：1996-10-14
申请人： HITACHI LTD , HITACHI PROCESS COMPUTER ENG
发明人： YAMADA TSUTOMU , KUROSAWA KENICHI , MASUI KOJI , OHASHI AKIHIRO , NAGAYAMA HISAO
IPC分类号： G06F12/02 , G06F12/06 , G06F13/36 , G06F15/17 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To obtain an address converting circuit with a small circuit scale which gives flexibility to access by converting a part of an address and outputting it to a local bus. SOLUTION: A processor 1, a main storage 3, and a local bus 21 are connected to one another by a memory controller 2. The address converting circuit 100 bypasses a part of AC 14 between the local bus 12 and a system bus 16. Then the address converting circuit 100 consists of a conversion part 110, a conversion control part 130, and a bus state machine part 150, and the bus state machine part 150 monitors the state of the local bus 12 and the conversion control part 130 determines whether or not address conversion is done and the direction of a two-way AD signal passing through the conversion part according to the state of the local bus 12. For access from the system bus 16, the memory controller 2 recognizes the address converted by the address converting circuit 110 and gains access to the main storage 3.

34. 发明专利

JPH09293059A DECENTRALIZED SYSTEM AND ITS OPERATION MANAGEMENT METHOD 失效
公开(公告)号：JPH09293059A
公开(公告)日：1997-11-11
申请号：JP10529296
申请日：1996-04-25
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , OOKURA TAKANORI , TAKEWA HIDEHITO , KUROSAWA KENICHI , KANEKO SHIGENORI
IPC分类号： G06F11/20 , G06F9/50 , G06F15/16
摘要： PROBLEM TO BE SOLVED: To provide the high-reliability decentralized system which carries on the operation of one server node by another redundant node even if trouble occurs to the operation of the server node. SOLUTION: The server node 3000 etc. is provided with an operation node 3200 which manages operations A and B, one by one. For all operations performed by the decentralized system, an in-system operation information managing means 1100 is provided which manages operation states, standby system operation information, and information on a communication path to a client. A client node 2000 is provided with a redundant communication path establishing means 2200 which establishes a communication path even for a standby system operation of the operation A and makes it 'stand by' when establishing a communication path so as to utilize the operation A. An in-use/ standby communication path is reported by a communication path reporting means 2300 to the operation information managing means. Further, this system is provided with a communication path switching means 2200 that judges which of the in-operation and standby system is performing the operation and selects the communication path for the operation in execution.

35. 发明专利

JPH09171464A PARALLEL PROCESSOR 失效
公开(公告)号：JPH09171464A
公开(公告)日：1997-06-30
申请号：JP1220997
申请日：1997-01-27
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , TANAKA SHIGEYA , NAKATSUKA YASUHIRO , BANDO TADAAKI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To make it possible to normally operate almost all conventional software by performing a parallel processing for plural instructions or performing successive processings for continuous instructions. SOLUTION: In an IF stage, the two instructions designated by a program counter are read when the value of the processing state flag PE 116 of a processor status register 103 is on and the instructions are set to first and second instruction registers 104 and 105, respectively. When the both of these first and second instruction registers 104 and 105 are not branching instructions, a previous program count value +2 is set to a latch 102 in the program counter. At the time of a branching, a branching address is calculated and the address is set to the program counter. At the time of a condition branching, the propriety of the branching is judged by the flag information 120 and 119 from first and second arithmetic units 108 and 109 and a program counter arithmetic unit 101 is controlled by using a branching designation address information 121 and branching control information 122.

36. 发明专利

JPH0855095A DUPLEX INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH0855095A
公开(公告)日：1996-02-27
申请号：JP12519795
申请日：1995-05-24
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , OGURA MAKOTO , KUROSAWA KENICHI , YAMAGUCHI SHINICHIRO , MIYAZAKI YOSHIHIRO , OGURO HIROSHI
IPC分类号： G06F11/20 , G06F15/16
摘要： PURPOSE:To shorten the memory copy time to improve the reliability of the system by using plural data transfer devices to the other system to take partial charge of memory copy. CONSTITUTION:When any faults don't occur in data transfer paths 700 to 703 in two computer systems 10 and 11 which are normally operated synchronously with each other, data transfer paths 700 to 703 are made take partial charge or data transfer for memory copy. That is, the throughput of data transfer for memory copy is four times as high as that of the use of one data transfer path if four data transfer paths 700 to 703 are provided. If one of data transfer paths 700 to 703 is faulty, the other normal data transfer paths are used to transfer data. Thus, the time required for memory copy is shortened, that is, the time of operation with one system till the completion or resynchronization is shortened, and the reliability of the system is improved.

37. 发明专利

JPH06266574A SYSTEM CONTROL LSI FOR HIGH-RELIABILITY COMPUTER AND COMPUTER SYSTEM USING THE SAME 失效
公开(公告)号：JPH06266574A
公开(公告)日：1994-09-22
申请号：JP5677793
申请日：1993-03-17
申请人： HITACHI LTD
发明人： KUROSAWA KENICHI , IWAMOTO HIROSHI , OGURO HIROSHI , NAKAMIGAWA TETSUAKI , MORIOKA MICHIO
IPC分类号： G06F11/18 , G06F12/08 , G06F12/10 , G06F15/177
摘要： PURPOSE:To provide the high-reliability computer system and system control LSI for continuing processing as long as possible corresponding to the fault level of a processor in a system provided with duplexed processors. CONSTITUTION:A master processor P0 and a checker processor P1 incorpolates a fault factor register Eri and a cache state register DREGi, and the system control LSI (SC) is provided with master checker control circuits (MCC and WSEL), compare circuit CMP, check clutch CL and processor reset register PRST. Even when a TLB fault, instruction cache fault or a data cache line fault in a clean state is generated, in this system, the two pairs of processors are synchronized again by resetting the processors so as to continue the processing. Thus, even when any non-coincidence is generated in the output of the processor, the processing can be continued corresponding to the fault level without system down.

38. 发明专利

JPH0557191B2 失效
公开(公告)号：JPH0557191B2
公开(公告)日：1993-08-23
申请号：JP1125583
申请日：1983-01-28
申请人： HITACHI LTD , HITACHI ELEVATOR ENG & SERVICE
发明人： KUROSAWA KENICHI , OKA TAKAAKI , YONEDA KENJI , UEJIMA TAKAAKI , MIURA MASAKI
IPC分类号： B66B1/18 , B66B3/00

39. 发明专利

JPH0517152B2 失效
公开(公告)号：JPH0517152B2
公开(公告)日：1993-03-08
申请号：JP13337382
申请日：1982-07-29
申请人： HITACHI LTD
发明人： YONEDA KENJI , SAKATA KAZUHIRO , SAKAI YOSHIO , KUROSAWA KENICHI
IPC分类号： B66B3/00 , B66B1/18

40. 发明专利

JPH0476913B2 失效
公开(公告)号：JPH0476913B2
公开(公告)日：1992-12-04
申请号：JP19245282
申请日：1982-11-04
申请人： HITACHI LTD
发明人： MIURA MASAKI , KUROSAWA KENICHI , KUZUNUKI SOSHIRO , YONEDA KENJI , HIRASAWA KOTARO
IPC分类号： B66B1/18

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