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1. 发明专利

JP2011138852A Lsi, failsafe lsi for railway, electronic device, and electronic device for railway 有权
标题翻译： LSI，用于铁路的FAILSAFE LSI，电子设备和用于铁路的电子设备
公开(公告)号：JP2011138852A
公开(公告)日：2011-07-14
申请号：JP2009296659
申请日：2009-12-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMIGAWA TETSUAKI , SHIMAMURA KOTARO , SAKUYAMA HIDEO , TAKEHARA TAKESHI
IPC分类号： H01L21/822 , G06F11/18 , G06F15/78 , H01L21/82 , H01L27/04
CPC分类号： H03K19/0075 , G05B9/03 , G06F11/1641 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L24/48 , H01L27/0207 , H01L27/11898 , H01L2027/11875 , H01L2027/11877 , H01L2027/11879 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To solve such a problem that, in the technique of the conventional failsafe LSIs, the arrangement of processors and comparators in chips is mentioned, but the arrangement of package signal pins is not mentioned, and also, the correspondence to various peripheral circuits and high-speed external memories is not considered. SOLUTION: An internal interface in which outputs from two processors are collated into one is connected to a common system internal bus. A plurality of external interface circuits are connected to the common system internal bus. Furthermore, signal pins related to two systems are disposed at opposing corners of a package while signal pins related to the common system are disposed therebetween. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题为了解决在现有的故障保护LSI的技术中提到了芯片中的处理器和比较器的布置的问题，但是没有提及封装信号引脚的布置，而且，不考虑与各种外围电路和高速外部存储器的对应关系。
解决方案：将两个处理器的输出整合为一个的内部接口连接到公共系统内部总线。多个外部接口电路连接到公共系统内部总线。此外，与两个系统相关的信号引脚设置在封装的相对的角处，而与公共系统相关的信号引脚设置在它们之间。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2008171198A Image processing system 有权
标题翻译：图像处理系统
公开(公告)号：JP2008171198A
公开(公告)日：2008-07-24
申请号：JP2007003714
申请日：2007-01-11
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMIGAWA TETSUAKI , MURAMATSU SHOJI
IPC分类号： G06T1/20 , G06F15/167
CPC分类号： G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide an image processing system capable of effectively synchronizing the processing by a CPU or a dedicated processing device and the data passing processing between pipeline stages.
SOLUTION: The image processing system comprises a first image processing device 20 for reading a first image written in a main memory 3, and after providing first processing to it, writing it to the main memory as a second image, a second image processing device 40 for reading the second image written to the main memory, and after providing second processing to it, writing it to the main memory as a third image, and an address monitoring device 10 for monitoring an address of the image written to the main memory, and starting the first processing when the address becomes a predetermined first value, and the second processing when the address become a predetermined second value.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够使CPU或专用处理装置的处理有效地同步的处理系统以及流水线级之间的数据通过处理。解决方案：图像处理系统包括用于读取写入主存储器3中的第一图像的第一图像处理装置20，并且在对其提供第一处理之后，将其作为第二图像写入主存储器，第二图像处理装置40，用于读取写入主存储器的第二图像，并且在对其进行第二处理之后，将其作为第三图像写入主存储器;以及地址监视装置10，用于监视写入主存储器的图像的地址存储器，并且当地址变为预定的第一值时开始第一处理，并且当地址变为预定的第二值时进行第二处理。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2006004100A Railroad information distribution system 审中-公开
标题翻译：铁路信息分配系统
公开(公告)号：JP2006004100A
公开(公告)日：2006-01-05
申请号：JP2004178673
申请日：2004-06-16
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMIGAWA TETSUAKI , FUTAGAWA MASAYASU , HOTTA MASATO
IPC分类号： B61L25/02 , G06Q50/00 , G06Q50/30
摘要： PROBLEM TO BE SOLVED: To provide an information distribution system capable of bridging between passengers and a railroad enterprise and making profits for both the sides by allowing the railroad enterprise to directly know passenger's intentions, i.e. how the passengers themselves want to behave. SOLUTION: Information service corresponding to user's intentions is provided and the intentions are utilized for operation management. In order to improve a flow of information which is a one-way flow from the railroad enterprise side to the passenger side in a conventional system is improved to bidirectional flow and transmit passenger's intentions to the railroad enterprise side, a means for returning passenger's intentions is included in information provided from an information distribution server to passengers, service based on the intentions is provided to the passengers and the information distribution server sends collected passenger's intentions to an operation management system. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过允许铁路企业直接了解乘客的意图，即乘客本身想要行为的方式，提供能够搭乘乘客和铁路企业之间桥接的信息分配系统，为双方利益。
解决方案：提供与用户意图对应的信息服务，并将其用于运营管理。为了改善在常规系统中从铁路企业侧到乘客侧的单向流动的信息流被改进为双向流动并将乘客的意图传递给铁路企业侧，返回乘客意图的手段是包括在从信息分发服务器向乘客提供的信息中，基于该意图提供给乘客的服务，并且信息分发服务器将收集的乘客的意图发送到操作管理系统。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2002259155A MULTIPROCESSOR SYSTEM 失效
公开(公告)号：JP2002259155A
公开(公告)日：2002-09-13
申请号：JP2001050484
申请日：2001-02-26
申请人： HITACHI LTD
发明人： NAKAMIGAWA TETSUAKI , SAITO MASAHIKO , YOKOYAMA TAKANORI , ONO HIROSHI
IPC分类号： G06F11/20 , G06F9/46 , G06F9/48 , G06F11/26 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To solve a problem that the conventional hot standby system has a limit to shorten failure detecting time since it detects the failure by interruption of heartbeat. SOLUTION: In this computer system constituted by providing and multiplexing a plurality of computers to be operated as switching a plurality of operating systems, the respective computers 10, 11 have a plurality of OSs under an OS switching program, monitors a software failure of an application OS 510 by a monitoring OS 520 and when the failure is generated, immediately informs other system of the failure via an exclusive communication means from an inter-system monitoring task 522. Handover time is shortened since the failure is detected without waiting for the interruption of the heartbeat.

5. 发明专利

JPH08190494A HIGH-RELIABILITY COMPUTER WITH DUAL PROCESSORS 失效
公开(公告)号：JPH08190494A
公开(公告)日：1996-07-23
申请号：JP239095
申请日：1995-01-11
申请人： HITACHI LTD
发明人： YAMAGUCHI SHINICHIRO , NAKAMIGAWA TETSUAKI , MIYAZAKI NAOTO , MIYAZAKI YOSHIHIRO , HIUGA KAZUHIRO , ISHIKAWA SUKETAKA , OGURO HIROSHI
IPC分类号： G06F11/18
摘要： PURPOSE: To provide a high-reliability computer which is highly common with general-purpose computers and also high in performance-cost ratio. CONSTITUTION: The computer consisting of two CPUs 1A and 1B of the same constitution and an input/output device has an identical-frequency, in-phase clock supply means for both the CPUs 1A and 1B, a doubled controller DSBA 2 which connects both the CPU 1A and 1B to the input/output device, and a communication means which sends and receives the states of the CPUs, etc., between both the CPUs 1A and 1B. The DSBA 2 selects an output instruction from one CPU and sends it to the input/output device, sends a response from the input/output device to both the CPUs 1A and 1B, informs the memories in the CPUs 1A and 1B of memory access from the an input/output device, and selects a memory access response from one CPU and sends it to the input/ output device. If a fault occurs in the CPU 1A or 1B, the DSBA 2 automatically disconnects the faulty CPU and continues to execute a program with the sound CPU. Consequently, high reliability is easily obtained at a low cost and a fault position can be replaced during on-line transaction execution.

6. 发明专利

JPH06274461A MULTIPROCESSOR SYSTEM HAVING CACHE MATCHING ENSURING FUNCTION VALIDATING RANGE DESIGNATION 失效
公开(公告)号：JPH06274461A
公开(公告)日：1994-09-30
申请号：JP5833293
申请日：1993-03-18
申请人： HITACHI LTD
发明人： MORIOKA MICHIO , KUROSAWA KENICHI , NAKAMIGAWA TETSUAKI , ISHIKAWA SUKETAKA
IPC分类号： G06F12/08 , G06F12/10 , G06F15/16 , G06F15/163 , G06F15/17
摘要： PURPOSE:To provide a high speed system in which cache matching assurance validating the reduction of communicating amounts among processors can be attained, in a large-scaled multiprocessor system. CONSTITUTION:Attribute information 223 for designating the range of the cache matching assurance is held in an address conversion buffer 220 incorporated in a processor 200, and a cache matching assurance control mechanism 310 which discriminates whether the cache matching assurance is operated only in a cluster 100, or the cache matching assurance is operated to entire cache memories 240 in the system according to the cache matching assurance attribute information 223 is provided in a processor memory interface device 300. Therefore, the range where the cache matching assurance is operated can be designated according to the feature of the data, and the delay of the cache matching assurance control can be sharply improved. Also, it is not necessary to broadcast the data to the entire processors in the system each time memory reading/ writing is operated, and the communicating amounts among processor can be sharply reduced.

7. 发明专利

JP2012123719A Programmable controller 有权
标题翻译：可编程控制器
公开(公告)号：JP2012123719A
公开(公告)日：2012-06-28
申请号：JP2010275719
申请日：2010-12-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMIGAWA TETSUAKI , KAMIWAKI TADASHI , YAMADA TSUTOMU , SHIRAISHI MASAHIRO , OTANI TATSUYUKI
IPC分类号： G06F9/32 , G06F12/08
CPC分类号： G06F9/30018 , G06F9/30043
摘要： PROBLEM TO BE SOLVED: To prevent suspension of pipeline processing by read-modify-write which frequently occurs in a programmable controller with a bit operation processor for ladder language.SOLUTION: A programmable controller provides; a pipeline stage EX (an execution stage) performing a bit operation and merging of bit data behind a pipeline stage R (a read stage) loading object data of read-modify-write in a buffer register and keeping an address of the object data in a register file 152; and behind that, a pipeline stage W (a write stage) storing the merging result in the address stored in the read stage R.
摘要翻译：要解决的问题：通过用于梯形图语言的位操作处理器的可编程控制器中经常发生的读取 - 修改 - 写入来防止流水线处理的中止。解决方案：可编程控制器提供; 执行位操作的流水线级EX（执行级），并且在流水线级R（读取级）之后的位数据合并在缓冲寄存器中加载读取 - 修改 - 写入的对象数据并保存对象数据的地址寄存器文件152; 并且在此之后，将存储在读取阶段R中的地址中的合并结果存储的流水线阶段W（写入阶段）。（C）2012，JPO＆INPIT

8. 发明专利

JP2009086789A Parallel image processor 审中-公开
标题翻译：并行图像处理器
公开(公告)号：JP2009086789A
公开(公告)日：2009-04-23
申请号：JP2007252959
申请日：2007-09-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： NAKAMIGAWA TETSUAKI , TAKAHASHI NOBUTAKA , MURAMATSU SHOJI
IPC分类号： G06T1/20 , G06F9/50
摘要： PROBLEM TO BE SOLVED: To flexibly combine parallel processing with pipeline processing in order to increase the speed of an image recognition system through the efficient use of a plurality of image processors.
SOLUTION: A scheduler for managing a plurality of image processing commands in a batch is provided with a determination means for allocating one image processing command that can be processed in parallel to a plurality of image processors, and a means for creating separated processing addresses.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了灵活组合并行处理与流水线处理，以通过有效使用多个图像处理器来提高图像识别系统的速度。解决方案：一批用于管理多个图像处理命令的调度器具有一个确定装置，用于分配一个可与多个图像处理器并行处理的图像处理命令，以及一个用于创建分离处理的装置地址版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2004326342A Modularized computer system and i/o module 有权
公开(公告)号：JP2004326342A
公开(公告)日：2004-11-18
申请号：JP2003118714
申请日：2003-04-23
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMADA TSUTOMU , NAKAMIGAWA TETSUAKI , ENDO HIROMICHI , MATSUMOTO NORITAKE , KASASHIMA HIROKAZU
IPC分类号： G06F13/14 , G06F3/00 , G06F13/10 , G06F13/40
CPC分类号： G06F13/4095
摘要： PROBLEM TO BE SOLVED: To identify the type of an I/O module connected to an arithmetic processing module, without dependence on a specific bus system. SOLUTION: I/O modules connected in layers to the arithmetic processing module 1 via connectors each have a module-exclusive selection part. The module-exclusive selection part discriminates to be effective only a module selection signal input from a terminal in the same position on an arithmetic processing module side connector, and correspondingly outputs identification information on the associated I/O module to a given connector terminal, so that the arithmetic processing module can acquire the I/O module identification information from the given connector terminal, without dependence on a specific bus system. The simple module selection circuit system wherein module selection signals sequentially output from the arithmetic processing module are input into the terminals in the same position on the arithmetic processing module side connectors in the connection order of the I/O modules can select respective specific I/O modules. COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2000078122A Asynchronous signal synchronizing type control circuit 审中-公开
标题翻译：异步信号同步型控制电路
公开(公告)号：JP2000078122A
公开(公告)日：2000-03-14
申请号：JP24469398
申请日：1998-08-31
申请人： Hitachi Ltd , Hitachi Process Comput Eng Inc , 日立プロセスコンピュータエンジニアリング株式会社 , 株式会社日立製作所
发明人： FUKUMARU HIROAKI , OGAWA HISAO , AZUMA AKIO , NAKAMIGAWA TETSUAKI , OKAZAKI SHUICHI
IPC分类号： H04L7/00 , H04L12/02
摘要： PROBLEM TO BE SOLVED: To attain acceleration while reducing synchronizing time loss generated when synchronizing asynchronous signals by transiting to a state transiting state in the case of generating no metha stable corresponding to a signal converging the metha stable from the destination of transition at the time of metha stable generation. SOLUTION: The number of flip-flops for receiving an asynchronous level signal, using the output as the input of a synchronizing type control signal and changing at the state transition time of a control signal caused by a signal having the possibility of metha stable generation is made into one. When the input of the control circuit is turned into metha stable state, all the state transition destinations having the possibitliy of generation are defined as metha stable convergence waiting state and corresponding to the signal converging the metha stable from the transition destination at the time of metha stable generation, the state is transited into state transiting state in the case of generating no metha stable. This is appropriately used for optical communication equipment for matching the states of two electric buses A20a and B20b repeated by an optical fiber 50, for example.
摘要翻译：要解决的问题：为了获得加速，同时减少在异步信号通过转移到状态转移状态时产生的同步时间损失，在不产生对应于在从 metha稳定一代。解决方案：使用输出作为同步型控制信号的输入并且在由具有metha稳定生成的可能性的信号引起的控制信号的状态转变时间处的接收异步电平信号的触发器的数量是制成一体。当控制电路的输入变成麦克稳定状态时，具有产生可能性的所有状态转换目的地被定义为均衡稳定收敛等待状态，并且对应于在metha时从转换目的地汇聚来自metha的信号的信号在稳定发电的情况下，国家在不产生稳定的情况下转入国家过境状态。这适合用于例如用于匹配由光纤50重复的两个电总线A20a和B20b的状态的光通信设备。

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