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31. 发明专利

JPS61141155A Solder-base electrode 失效
标题翻译：焊接电极
公开(公告)号：JPS61141155A
公开(公告)日：1986-06-28
申请号：JP26275984
申请日：1984-12-14
申请人： Hitachi Ltd
发明人： MORI TAKAO , MIZUISHI KENICHI , ONOZATO AKIMASA , YUKI FUMIO , IMAI KUNINORI
IPC分类号： H01L21/60 , H01L21/92
CPC分类号： H01L2224/11 , H01L2224/13099 , H01L2924/01022 , H01L2924/01024 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/00012
摘要： PURPOSE:To contrive accomplishment of high reliability of a solder electrode part as well as to enable to perform a compound semiconductor process in a clean atmosphere by a method wherein the Ni having the high mechanical coupling a strength for solder material and thermally stable property is used as the base material. CONSTITUTION:The electrode structure, consisting of Cr or Ti as the first layer (adhesive layer) 104, Ni as the second layer of intermediate metal layer 105, and Au as the third layer (anti-oxidation layer) 106 as the third layer, is optimum as the base electrode for solder. When the GaAs LSI flip chip manufactured by adopting the above-mentioned structure is adhered to a ceramic wiring substrate, an SiO2 protective film 203 is formed on the GaAS LSI chip 201, and then a contact hole is formed on a chip-side wiring layer 202. Subsequently, a Cr or Ti layer 204, an Ni layer 205 and an Au layer 206 are successively vapor-deposited, and a solder-base electrode is formed. Then, after the electrode is formed into the prescribed shape by performing a photoetching, a Pb/Sn continuous vapor-deposition is conducted through a metal vapor- deposition mask, and a solder layer is formed.
摘要翻译：目的：为了实现焊接电极部件的高可靠性，以及能够通过其中使用具有高机械耦合的Ni具有焊料材料的强度和热稳定性能的方法在清洁的气氛中进行化合物半导体工艺作为基材。构成：由作为第一层（粘合剂层）的Cr或Ti，作为中间金属层105的第二层的Ni和作为第三层的第三层（抗氧化层）106的Au构成的电极结构，作为焊料的基极是最佳的。当采用上述结构制造的GaAs LSI倒装芯片被粘附到陶瓷布线基板上时，在GaAS LSI芯片201上形成SiO 2保护膜203，然后在芯片侧布线层随后，依次气相沉积Cr或Ti层204，Ni层205和Au层206，形成焊料基电极。然后，通过进行光刻，在电极形成规定形状之后，通过金属蒸镀掩模进行Pb / Sn连续气相沉积，形成焊料层。

32. 发明专利

JPS59210686A Semiconductor laser device 失效
标题翻译：半导体激光器件
公开(公告)号：JPS59210686A
公开(公告)日：1984-11-29
申请号：JP7849684
申请日：1984-04-20
申请人： Hitachi Ltd
发明人： DOI KOUNEN , HIRAO MOTONAO , NAKAMURA MICHIHARU , TSUJI SHINJI , MORI TAKAO
IPC分类号： H01L21/208 , H01S5/00 , H01S5/227
CPC分类号： H01S5/227 , H01S5/2275
摘要： PURPOSE:To remove a crystal defect induced in a buried layer being in contact with a buffer layer in a laser device, and to manufacture a laser having excellent reproducibility by forming the buried layer in a crystal growth layer of a four-element composition. CONSTITUTION:A buffer layer 2, an active layer 3, a clad layer 4 and a cap layer 5 are grown on a semiconductor substrate 1 in succession through a slide epitaxial method. When forming the each layer 2-5, the composition of a solution is brought close to that of InP, and a grating constant matching with InP is used. Each layer 2-5 is formed as an InP buffer layer 2 in predetermined thickness, an active layer 3 of a four-element composition, an InP clad layer 4 and a cap layer 5 of the four-element composition by the composition of the solution, the layer 3 shall be of In0.74Ga0.26As0.57P0.43, and the layer 4 shall be of In0.84 Ga0.16As0.36P0.64. A first In0.99Ga0.01As0.02P0.98 buried layer 6, an N type InP second buried layer 7 and an In0.74Ga0.26As0.57P0.43 cap layer 8 are shaped through mesa etching, and crystal defects induced in the layers 6, 7 are prevented.
摘要翻译：目的：去除在与激光装置中的缓冲层接触的掩埋层中感应的晶体缺陷，并且通过在四元素组成的晶体生长层中形成掩埋层来制造具有优异再现性的激光。构成：缓冲层2，有源层3，覆盖层4和覆盖层5通过滑动外延法连续生长在半导体衬底1上。当形成每个层2-5时，溶液的组成接近于InP的组成，并且使用与InP匹配的光栅常数。每个层2-5通过溶液的组成形成为具有预定厚度的InP缓冲层2，四元素组合物的有源层3，四元素组合物的InP包覆层4和覆盖层5 ，层3应为In 0.74Ga0.26As0.57P0.43，第4层应为In 0.84 Ga 0.16 As 0.36 P 0.64。第一In0.99Ga0.01As0.02P0.98掩埋层6，N型InP第二掩埋层7和In0.74Ga0.26As0.57P0.43覆盖层8通过台面蚀刻成形，并且在层中引起晶体缺陷 6，7。

33. 发明专利

JPS5887890A SEMICONDUCTOR LASER DEVICE 失效
公开(公告)号：JPS5887890A
公开(公告)日：1983-05-25
申请号：JP18540781
申请日：1981-11-20
申请人： HITACHI LTD
发明人： TSUJI SHINJI , NAKAYAMA YOSHINORI , HIRAO MOTONAO , MORI TAKAO , MIZUISHI KENICHI , NAKAMURA MICHIHARU
IPC分类号： H01S5/00 , H01S5/026 , H01S5/062 , H01S5/227
摘要： PURPOSE:To prevent the breakdown of an end surface which leads to a decisive destruction of an element, by forming a pnpn structure inside crystals in parallel to a beam-emitting part, and by providing a gate electrode outside the element so that a current flowing to the beam-emitting part can be controlled by a thyristor operation. CONSTITUTION:Ga1-xAlxAs 22 forming a first clad layer, GaAs 1 forming an active layer, and Ga1-yAlyAs 21 forming a second clad layer are superposed sequentially on an n type GaAs substrate 4. Next, a p type Ga1-zAlzAs layer 32 and an n type Ga1-z, Alz, As layer 31 are superposed on both sides of a stripe-shaped semiconductor laminate region. Then, a region 7 of diffused impurity, such as Zn, is formed by a well- known method. A pnpn structure is constituted by these two layers, the GaAs substrate and the p type diffused region 7, including a buried region. By using a well-known method of diffusin or ion implantation, a p region 8 is formed so as to reach the p type GaAlAs layer 32, a gate electrode 9 is provided in addition to usual electrodes 5 and 6, and thereby an element of the present invention is obtained. In this element, a trigger current is made to flow to the gate electrode 9 to put the part of the pnpn structure in an ON state, and thereby a current flowing through the active region 1 can be restricted.

34. 发明专利

JPS5877259A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5877259A
公开(公告)日：1983-05-10
申请号：JP17566881
申请日：1981-11-04
申请人： HITACHI LTD
发明人： SAITOU KATSUTOSHI , MORI MITSUHIRO , MORI TAKAO , SATOU NOBU , KOBAYASHI MASAYOSHI , CHIBA KATSUAKI , KATOU HIROSHI , KOBAYASHI MASAMICHI
IPC分类号： H01L29/43 , H01L21/28 , H01L29/45 , H01S5/00 , H01S5/042
摘要： PURPOSE:To prevent the separation of a wiring of semiconductor device by a method wherein a binder of thin film of Ti, Cr, etc., having favorable adhesion is provided between a barrier metal of Mo, etc., and the metal wiring. CONSTITUTION:An N type GaAlAs clad layer 6, an N type GaAlAs active layer 7, a P type GaAlAs clad layer 8, and an N type GaAs layers 9 are formed on an N type GaAs substrate 1 according to the liquid phase growth method, a mask 10 having a slender opening of 2mum width is provided on the layer 9, and Zn is diffused to form a P type layer 11. Then an ohmically connecting layer 12 of Ti or Cr, an Mo barrier metal layer 4, and a binder layer 13 of Ti or Cr are evaporated in order, and an electrode wiring layer 4 of Au or Ag is adhered. After thickness of the substrate 1 is regulated to about 100mum, an AuGe layer 14, an Ni layer 15 are evaporated, a binder layer 13 of Ti or Cr is accumulated, and an electrode 5 of Au or Ag is adhered to complete. By this constitution, the separation of the electrode wiring can be prevented.

35. 发明专利

JPS56157082A SEMICONDUCTOR LASER DEVICE AND MANUFACTURE 失效
公开(公告)号：JPS56157082A
公开(公告)日：1981-12-04
申请号：JP6061980
申请日：1980-05-09
申请人： HITACHI LTD
发明人： HIRAO MOTONAO , DOI KOUNEN , NAKAMURA MICHIHARU , TSUJI SHINJI , MORI TAKAO
IPC分类号： H01S5/00 , H01S5/227
摘要： PURPOSE:To decrease a threshold current value and improve a luminous efficiency by a method wherein a surface of a buried layer is situated on the part upper than a surface layer formed on an active region. CONSTITUTION:A cladding layer 22 of n-InP, an active layer 23 of InGaAs, a cladding layer 24 of p-InP and the surface layer 25 of p-InGaAs are formed in layers on an InP substrate 21 of n-conductive type to construct a mesa region. The n-InP buried layer 26 is formed in contact with the side wall surfaces of the semiconductor layers 22-25 in a mesa-etched region. A liquid phase growth improved layer 27 of the n-InGaAs is formed on the buried layer 26. An oxide film 28 is formed and in addition, a metallic electrode 29 is formed on the liquid phase growth improved layer 27. When a prescribed voltage is applied between the electrode 29 and a bottom electrode on the substrate side 21, the laser rays are radiated.

36. 发明专利

JPH0697237A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0697237A
公开(公告)日：1994-04-08
申请号：JP24171792
申请日：1992-09-10
申请人： HITACHI LTD , HITACHI CABLE
发明人： MORI TAKAO , YOSHIDA SATOSHI , NISHIMUKAI TADAHIKO , YAMAGUCHI KENJI
IPC分类号： H01L21/60 , H01L23/495 , H01L23/50 , H01L25/04 , H01L25/18
摘要： PURPOSE:To provide the title semiconductor device and manufacturing method thereof effective for the rapid tape carrier packaging step of semiconductor element having multiple terminals. CONSTITUTION:The second film carriers 4b are overlapped with the first film carriers 4a to be laminated using a bonding agent 10. The metallic leads 3a and 3b on mutual film carriers are arranged on respective gaps without coming into contact and intersection with one another while the lead ends thereof are to be bonded onto the electrodes 2 of a semiconductor element 1. The metallic leads 3 are previously formed on the film carriers 4 by etching step so that the lead connecting pitches may be effectively reduced by laminating the multiple film carriers with one another.

37. 发明专利

JPH0513604A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0513604A
公开(公告)日：1993-01-22
申请号：JP28757091
申请日：1991-11-01
申请人： HITACHI LTD
发明人： MORI TAKAO , TOKUDA MASAHIDE , FUJITA YUJI , MIZUISHI KENICHI , HAYASHIDA TETSUYA , HATSUDA TOSHIO
IPC分类号： H01L23/02 , H01L23/04
摘要： PURPOSE:To relieve stress generated in lead joints of a semiconductor chip due to assembly of a semiconductor device, testing steps, and variations in atmosphere temperature. CONSTITUTION:A protection cap which seals a semiconductor chip 1 is separated into a lid plate 9 and a support frame 8. The support frame 8 is disposed on the outer periphery of a wiring board 3 loaded with the semiconductor chip 1, and the lid plate 9 is fixed with solder by the top of this support frame 8 and the rear of the semiconductor chip 1 to seal it.

38. 发明专利

JPH03220762A THREE-DIMENSIONAL LAMINATION DEVICE 失效
公开(公告)号：JPH03220762A
公开(公告)日：1991-09-27
申请号：JP1492690
申请日：1990-01-26
申请人： HITACHI LTD
发明人： MORI TAKAO , KATO TAKESHI , FUJITA YUJI , MIZUISHI KENICHI
IPC分类号： H05K1/18 , H01L27/00
摘要： PURPOSE:To sharply shorten the wiring length while reducing an area of a wiring region by a method wherein elements on a board are signal-connected to elements on another board through terminals located on an inner edge of an opening part formed on the board. CONSTITUTION:A part of the boards 101 and 201 mounted with chips 104 and 204 is provided with an opening and wiring connection between the chips 104 and 204 on the upper and lower boards 101 and 201 is performed through this opening part. That is, the chips 104 and 204 mounted on the different boards 101 and 201 are mutually connected by the wiring layers 102, 202 formed on the respective boards 101, 201 and a lead terminal provided on the inner edge of the board opening part. The chips 104, 204 on the upper layer are made to connect to the chips 104, 204 of the lower layer located directly under the adjacent opening parts. Thereby, direct wiring between the chips 104, 204 on the upper and lower boards 101, 201 becomes possible not through leader wirings to the periphery of the boards 101 and 201 thus to enable the length of wiring and the area of a wiring region to be reduced.

39. 发明专利

JPH0212036B2 失效
公开(公告)号：JPH0212036B2
公开(公告)日：1990-03-16
申请号：JP17421283
申请日：1983-09-22
申请人： HITACHI LTD
发明人： TSUJI SHINJI , MORI TAKAO , DOI KONEN , TAKEDA YUTAKA , HIRAO MOTONAO , NAKAMURA MICHIHARU
IPC分类号： H01L21/308 , H01S5/00 , H01S5/227

40. 发明专利

JPS63186457A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPS63186457A
公开(公告)日：1988-08-02
申请号：JP1717087
申请日：1987-01-29
申请人： HITACHI LTD
发明人： MORI TAKAO , ONOZATO AKIMASA , MIZUISHI KENICHI
IPC分类号： H01L25/18 , H01L21/768 , H01L23/522 , H01L25/065 , H01L25/07 , H01L27/00 , H05K1/14
摘要： PURPOSE:To obtain a lamination-type semiconductor device wherein the area of an integrated circuit substrate occupied by a wiring region can be reduced, the total module can be miniaturized, and the high speed quality can be improved, by laminating a plurality of semiconductor integrated circuit substrates having a three-dimensional structure wherein wiring patterns for electric connection are formed on the surface, the rear, and the side surface. CONSTITUTION:A semiconductor integrated circuit substrate 10 has a three dimensional structure wherein wiring patterns 13 for electric connection are formed on the surface, the rear and the side surface. A plurality of the substrates are laminated, and wiring connection between each of the substrates 10 is made via the above-mentioned wiring patterns 13. For example, a computer module is constituted by stacking the integrated circuit substrates 10 of wafer scale. The central part of the substrate 10 is assigned to an active element region 11 constituted of memories and logic gates. These integrat ed circuit substrates 10 are stacked in 10-200 stages to realize a computer system. The wiring connection between the substrates 10 is made by mutually connecting the wiring layers 13 formed on the surface, the side surface, and the rear via soldering electrodes 14. Supporting bodies 15 are inserted between the substrates in order to prevent the deformation of the soldering electrodes 14.

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