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31. 发明专利

JP2001085553A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001085553A
公开(公告)日：2001-03-30
申请号：JP26155699
申请日：1999-09-16
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , MIWA TAKASHI , SHIRAI MASAYUKI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which has internal terminal arrangement with superior electrical characteristics, while effectively leading out electric wires between a semiconductor element and internal terminals. SOLUTION: This semiconductor device, which has external terminals arranged in a lattice shape, is characterized in that the interval 24 of 1st internal terminals arranged on a signal wiring layer 4 is an integral multiple of a 2nd internal terminal interval 25, a power terminal or ground terminal is arranged as a 1st internal terminal 22, and the rate of signal terminals arranged as 2nd internal terminals 23 is larger than the rate of signal terminals arranged in the signal wiring layer 4.

32. 发明专利

JP2000294684A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000294684A
公开(公告)日：2000-10-20
申请号：JP10232799
申请日：1999-04-09
申请人： HITACHI LTD
发明人： SHIRAISHI TOMOHIRO , SUWA MOTOHIRO , SHIRAI MASAYUKI , MIWA TAKASHI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To make the external form size of a multipin package small, by mounting a semiconductor chip at the center of the surface of a quadrangular package base, and arranging a plurality of bonding leads in plural rows on the same plane around the center of the package base. SOLUTION: A package board 1 is one where a semiconductor chip 7 being the chip of a semiconductor is to be mounted at the center of the surface of a quadrangular package base 2, and bonding leads (pads, surface electrodes) 3 are arranged in two rows on the same plane around the center of the package base 2. The interval between the bonding lead 3 at the end in one direction and the bonding lead 3 at the other end in other direction can be made half or under. Hereby, the external form size of the package board can be made small, and the external form size of the muitipin package can be made small, and it can be made into a package board of high performance and high reliability.

33. 发明专利

JP2000058579A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000058579A
公开(公告)日：2000-02-25
申请号：JP22035198
申请日：1998-08-04
申请人： HITACHI LTD
发明人： KUBOSONO MINORU , SUWA MOTOHIRO , MIWA TAKASHI , SHIRAI MASAYUKI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To reduce the effective inductance of signal lines in a semiconductor device and to improve the resistance to noise. SOLUTION: A semiconductor device 10 comprise a chip supporting substrate 2 for supporting a semiconductor chip 1, covered wires 3 for electrically connecting between the semiconductor chip 1 and leads 2a of the chip supporting substrate 2, insulating resin 4 for covering a wire joining part 3d of a covered wire 3 which is exposed by wire bonding, conductive resin 5 for sealing which covers the semiconductor chip 1 and the covered wires 3 which are electrically connected to it and is supplied with ground potential, and plural bumps 6 which are outer terminals. In this case, the exposed part of the conductive material in contact with the conductive resin 5 for supplying it with ground potential is a wire joining part 3c of the covered wire 3 which is wire bonded to a pad 1a for ground, and the covered wires 3 for signals are covered with conductive resin 5 which is supplied with ground potential by the wire joining part 3c.

34. 发明专利

JPH09298218A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09298218A
公开(公告)日：1997-11-18
申请号：JP11445296
申请日：1996-05-09
申请人： HITACHI LTD
发明人： TAKAHASHI HIROYUKI , ARAI TAKESHI , SUWA MOTOHIRO , KAMATA CHIYOSHI
IPC分类号： H01L21/60 , H01L21/321
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor device to deteriorate less in electric characteristics due to the reflection and radiation loss of signals by a method wherein a connecting part which connects a wiring layer to another wiring layer in a vertical direction is made tilted so as to make the vertical bent part of a transmission path obtuse. SOLUTION: A semiconductor chip 1 is hermetically sealed up in a laminated ceramic package 2, where the package 2 is composed of a board 3 where a multilayer interconnection is provided, a ceramic dam frame 4 provided in the periphery of the main surface of the board 3, and a cap 5 made of a gold- plated metal plate. The semiconductor chip 1 is hermetically sealed up in the package 2 in such a manner that the semiconductor chip 1 is bonded to the main surface of the board 3 through the intermediary of connectors 6 by being faced down, and after that, the cap 3 is fixed to the dam frame 4 to hermetically seal up the package. The connectors 6 are formed on pads 7 provided onto the main surface of the board 3 to transmit high-frequency signals, each composed of bump electrodes 6a and 6b which are made of gold or the like and laminated as staggered, and connected to the pads 7.

35. 发明专利

JPH07321150A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH07321150A
公开(公告)日：1995-12-08
申请号：JP11150894
申请日：1994-05-25
申请人： HITACHI LTD
发明人： TAKAHASHI HIROYUKI , SUWA MOTOHIRO
IPC分类号： H01L21/60 , H01L23/12
摘要： PURPOSE:To provide a technique for controlling a bump electrode which connects a semiconductor chip with a wiring board in characteristic impedance. CONSTITUTION:A semiconductor chip 2 is bonded on the prime surface of a package board 1 through the intermediary of bump electrodes 14 and 16 piled up in layers for the formation of an LSI package, wherein a capacitor element composed of an insulating tape 17 and a pair of conductor patterns 18a and 18b formed on both the sides of the insulating tape 17 is arranged between the bump electrodes 14 and 16, and one of the electrodes of the capacitor element is connected to a signal bump electrode, and the other electrode is connected to a grounding bump electrode.

36. 发明专利

JPH03131031A THIN-FILM WIRING, MANUFACTURE THEREOF AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03131031A
公开(公告)日：1991-06-04
申请号：JP26997289
申请日：1989-10-17
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , KAWABUCHI YASUSHI , ONUKI HITOSHI , SHIODA KATSUHIKO , FUKADA SHINICHI , NIHEI MASAYASU , MIYAZAKI KUNIO
IPC分类号： H01L21/3205 , H01L23/48 , H01L23/52
摘要： PURPOSE:To prevent the extension of a slit due to electro-migration by directly bringing a high melting-point substance layer having a specific melting point and a good conductive alloy layer into contact and unifying them. CONSTITUTION:A high melting-point substance layer 4 having the melting point of 1800K or higher and a good conductive alloy layer 5 are brought into contact directly and unified. That is, the high melting-point substance layer 4 and the good conductive alloy layer 5 are laminated directly without through an oxide film. These direct contact is formed by reducing a spontaneous oxide film shaped onto the high melting-point substance layer 4 by an additive added into the good conductive alloy layer 5 laminated onto the natural oxide film. When the alloy of an Al group is selected as the good conductive alloy 5, it is also effective that Cu, Pd, Hf, Ti, etc., are added into an Al wiring and a metallic element easy to be sufficiently bonded with oxygen such as Mg, Ca, Be, Na, and K is further added.

37. 发明专利

JPH02205031A SEMICONDUCTOR DEVICE AND WIRING FILM 失效
公开(公告)号：JPH02205031A
公开(公告)日：1990-08-14
申请号：JP2388789
申请日：1989-02-03
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , ONUKI HITOSHI , MIYAZAKI KUNIO
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To suppress rise in a wiring resistance and to prevent a malfunction from occurring by providing a diamond or sphalerite type structure at the top of an aluminum alloy wiring, and incorporating a substance in which its lattice constant is specified. CONSTITUTION:An AlP or GaP, ZnS, BeTe, etc., is laminated on an aluminum alloy wiring. The AlP of them has the same diamond structure as that of silicon in its crystalline structure, its lattice constant is 5.3-5.6Angstrom , and alternatively laminated wirings are employed. A contact hole is formed at a thermal oxide SiO2 film 3 by dry etching, aluminum alloy wiring 4 and an AlP film 5 are deposited thereon by a sputtering method, and patterned. Then, a passivation film 7 for protecting an element surface is deposited by a sputtering method. Subsequently, a hole is opened at the passivation film at the top of a bonding pad 8. A wafer formed in this state is heated and quickly cooled. The wafer formed in this manner is divided into respective chips, and bonded with bonding wirings 9 to be associated.

38. 发明专利

JPH02188922A ELECTRONIC DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02188922A
公开(公告)日：1990-07-25
申请号：JP602989
申请日：1989-01-17
申请人： HITACHI LTD
发明人： KAWABUCHI YASUSHI , ONUKI HITOSHI , MIYAZAKI KUNIO , SHIODA KATSUHIKO , SUWA MOTOHIRO , NIHEI MASAYASU , FUKADA SHINICHI , ITAGAKI TATSUO
IPC分类号： H01L23/52 , H01L21/3205
摘要： PURPOSE:To obtain a wiring material whose stress-migration-resistant property and electromigration-resistant property with reference to a wiring film are both excellent by a method wherein the wiring layer is constituted of a laminated film by an Al alloy and TiW or TiN and an Mg or Be film is formed at an interface between the Al alloy and the TiW or TiN. CONSTITUTION:In an electronics device having wiring films 4 to 6 on a semiconductor or insulator substrate 1, said wiring films 4 to 6 are constituted of a laminated film by an Al alloy 4 and TiW or Tin 5 and an Mg or Be film 6 is formed at an interface between the Al alloy 4 and the TiW or TiN 5. For example, an Al alloy 4 contains less than 5wt.% each of Pd, Pt, Si, Li, Be, Mg, Mn, Fe, Co, Ni, Cu, La and Ce and its remaining part is composed of Al, or TiW or TiN 5 contains less than 20wt.% of Mg or Be. when either Mg or Be or both are added in advance, the Al alloy 4 and the TiW or TiN 5 are laminated directly, and wiring films 4 to 6 are formed.

39. 发明专利

JP2002033424A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002033424A
公开(公告)日：2002-01-31
申请号：JP2000216802
申请日：2000-07-18
申请人： HITACHI LTD
发明人： MIWA TAKASHI , SUWA MOTOHIRO
IPC分类号： H01L23/12 , H01L21/60 , H01L23/36
摘要： PROBLEM TO BE SOLVED: To lower the cost of a heat diffusing plate, to prevent a blow hole from being formed, a wire from corroding due to water, etc., and to improve the heat radiating characteristics of the heat-diffusing plate. SOLUTION: This semiconductor device has an external terminal provided on the reverse surface of a base material, a semiconductor chip connected to the top surface of the base material, and the heat-diffusing plate thermally connected to the semiconductor chip. The heat-diffusing plate is composed of a heat radiator thermally connected to the semiconductor chip and a support which is formed integrally with the heat radiator, and the support is provided partially a the periphery of the heat radiator and adhered to the base material. In this constitution, the heat-diffusing plate can be formed integrally through simple machining, so the manufacturing of the heat-diffusing plate is facilitated and the cost is reduced. Further, the inside of the heat-diffusing plate is opened, so no blow hole is formed and water, etc., sticking on the semiconductor chip can easily be removed to prevent the wire from corroding, etc.

40. 发明专利

JP2001319989A PACKAGING STRUCTURE BODY OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001319989A
公开(公告)日：2001-11-16
申请号：JP2000134386
申请日：2000-05-08
申请人： HITACHI LTD
发明人： SUWA MOTOHIRO , MIWA TAKASHI , KURODA HIROSHI , SHIRAI MASAYUKI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To lengthen the life of the connection terminal of the packaging structure body of a BGA IC. SOLUTION: In the packaging structure body of the semiconductor device, a BGA IC 1 is connected to a packaging substrate 30 by a group of connection terminals 35 where each solder bump is formed by welding to each land 33. In the BGA IC 1, a group of external terminals 15 is arranged on the one main surface of a square flat-plate-shaped resin sealing package 10 where a semiconductor pellet 21 is sealed, and the solder bump projects in each of the external terminals 15. In this case, a four-cornered land 33a and an adjacent land 33b at a BGA IC packaging part 32 on the packaging substrate 30 are formed largely, thus thickening connection terminals 35a and 35b that are formed in the four-cornered land 33a and the adjacent land 33b at a land side for increasing durability, and hence lengthening the life.

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