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31. 发明授权

US6098141A Compact ISA-bus interface 有权
公开(公告)号：US6098141A
公开(公告)日：2000-08-01
申请号：US233230
申请日：1999-01-19
申请人： Mark Williams , Sukalpa Biswas
发明人： Mark Williams , Sukalpa Biswas
IPC分类号： G06F13/40 , G06F13/42 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4226 , G06F13/4027
摘要： An I/O interface, compatible with industry standards, for interfacing a host to a peripheral device. The interface includes a clock signal, a bus, an address latch enable signal, a peripheral device ready signal, a command signal, a device selected backoff signal, and a reset signal, resulting in an I/O interface capable of ISA-compatible operation with only 22 pins. Address, data, command, interrupt request, and DMA request information are communicated between the host and the peripheral device via a single bus by multiplexing the information on the bus using phasing techniques.

32. 发明授权

US5907857A Refresh-ahead and burst refresh preemption technique for managing DRAM in computer system 失效
标题翻译：刷新和突发刷新抢占技术，用于管理计算机系统中的DRAM
公开(公告)号：US5907857A
公开(公告)日：1999-05-25
申请号：US831261
申请日：1997-04-07
申请人： Sukalpa Biswas
发明人： Sukalpa Biswas
IPC分类号： G06F13/16 , G11C11/406 , G06F12/16
CPC分类号： G06F13/1636 , G11C11/406
摘要： A computer system refreshes dynamic memory in a burst, but allows other memory access requests to preempt a burst refresh before the burst completes. In another aspect, once a burst refresh begins, it is allowed to continue for a number of refresh cycles which is greater than the number of refresh cycles then due; that is, until a time when the number of refresh cycles due is negative. This technique, referred to herein as "refresh-ahead", effectively helps to shift memory refresh activity into periods of bus time which would otherwise be idle.
摘要翻译：计算机系统在突发中刷新动态存储器，但允许其他存储器访问请求在突发完成之前抢占突发刷新。在另一方面，一旦突发刷新开始，允许持续多个刷新周期，该刷新周期大于由此到期的刷新周期数; 也就是说，直到刷新周期数为负值的时间为止。这种技术（这里被称为“刷新前进”）有效地帮助将存储器刷新活动转移到否则将是空闲的总线时间。

33. 发明授权

US10573368B2 Memory system having combined high density, low bandwidth and low density, high bandwidth memories 有权
公开(公告)号：US10573368B2
公开(公告)日：2020-02-25
申请号：US16098916
申请日：2017-03-06
申请人： Sukalpa Biswas , Farid Nemati
发明人： Sukalpa Biswas , Farid Nemati
IPC分类号： G11C11/402 , G11C5/06 , G11C5/02 , G11C7/02 , G11C11/406 , H01L25/065 , H01L27/02
摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

34. 发明授权

US09311251B2 System cache with sticky allocation 有权
标题翻译：具有粘性分配的系统缓存
公开(公告)号：US09311251B2
公开(公告)日：2016-04-12
申请号：US13594932
申请日：2012-08-27
申请人： Sukalpa Biswas , Shinye Shiu , James Wang
发明人： Sukalpa Biswas , Shinye Shiu , James Wang
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/126 , Y02D10/13
摘要： Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and each line allocated in the system cache may be associated with a specific group ID. Also, each line may have a corresponding sticky state which indicates if the line should be retained in the cache. The sticky state is determined by an allocation hint provided by the requesting agent. When a cache line is allocated with the sticky state, the line will not be replaced by other cache lines fetched by any other group IDs.
摘要翻译：用于在存储器控制器内实现系统高速缓存的方法和装置。多个请求代理可以在系统高速缓存中分配高速缓存行，并且在系统高速缓存中分配的每一行可以与特定的组ID相关联。此外，每行可以具有相应的粘性状态，其指示该行是否应保留在高速缓存中。粘性状态由请求代理提供的分配提示确定。当缓存行被分配为粘性状态时，该行不会被任何其他组ID获取的其他高速缓存行所替代。

35. 发明授权

US08856459B1 Matrix for numerical comparison 有权
标题翻译：矩阵进行数值比较
公开(公告)号：US08856459B1
公开(公告)日：2014-10-07
申请号：US13313327
申请日：2011-12-07
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F13/18
CPC分类号： G06F13/385
摘要： A method and apparatus for utilizing a matrix to store numerical comparisons is disclosed. In one embodiment, an apparatus includes an array in which results of comparisons are stored. The comparisons are performed between numbers associated with agents (or functional units) that have access to a shared resource. The numbers may be a value to indicate a priority for their corresponding agents. The comparison results stored in an array may be generated based on comparisons between two different numbers associated with two different agents, and may indicate the priority of each relative to the other. When two different agents concurrently assert requests for access to the shared resource, a control circuit may access the array to determine which of the two has the higher priority. The agent having the higher priority may then be granted access to the shared resource.
摘要翻译：公开了一种利用矩阵存储数值比较的方法和装置。在一个实施例中，一种装置包括其中存储比较结果的阵列。在与可以访问共享资源的代理（或功能单元）相关联的数字之间执行比较。这些数字可能是指示其相应代理人的优先级的值。可以基于与两个不同代理相关联的两个不同数字之间的比较来生成存储在阵列中的比较结果，并且可以指示每个相对于另一个的优先级。当两个不同的代理同时断言访问共享资源的请求时，控制电路可以访问阵列以确定两者中的哪一个具有较高的优先级。然后可以授予具有较高优先级的代理对该共享资源的访问。

36. 发明授权

US08314807B2 Memory controller with QoS-aware scheduling 有权
标题翻译：具有QoS感知调度的内存控制器
公开(公告)号：US08314807B2
公开(公告)日：2012-11-20
申请号：US12883864
申请日：2010-09-16
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G09G5/39
CPC分类号： G06F9/5033 , G06F13/1668
摘要： In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to schedule operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline.
摘要翻译：在一个实施例中，存储器控制器包括多个端口。每个端口可能专用于不同类型的流量。在一个实施例中，可以为业务类型定义服务质量（QoS）参数，并且不同的业务类型可以具有不同的QoS参数定义。存储器控制器可以被配置为基于QoS参数调度在不同端口上接收的操作。在一个实施例中，当接收到具有较高QoS参数，经由边带请求和/或通过操作老化的后续操作时，存储器控制器可以支持QoS参数的升级。在一个实施例中，存储器控制器被配置为当操作流过存储器控制器管线时，减少对QoS参数的强调并且增加对存储器带宽优化的重视。

37. 发明授权

US08307236B2 Oversampling-based scheme for synchronous interface communication 失效
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US08307236B2
公开(公告)日：2012-11-06
申请号：US12912521
申请日：2010-10-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00 , G06F1/12 , G06F3/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

38. 发明授权

US08219880B2 Combined single error correction/device kill detection code 有权
标题翻译：组合单错误纠正/设备杀死检测码
公开(公告)号：US08219880B2
公开(公告)日：2012-07-10
申请号：US13246736
申请日：2011-09-27
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

39. 发明申请

US20120137090A1 Programmable Interleave Select in Memory Controller 审中-公开
标题翻译：内存控制器中的可编程交错选择
公开(公告)号：US20120137090A1
公开(公告)日：2012-05-31
申请号：US12955714
申请日：2010-11-29
申请人： Sukalpa Biswas , Hao Chen
发明人： Sukalpa Biswas , Hao Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/0638 , G06F12/1018
摘要： In one embodiment, a memory controller may be configured to perform a logic operation, such as a hash function, on selected address bits to produce a bit of channel or bank select. The selected address bits for each select bit may differ, and may be programmable in some embodiments. By combining selected address bits to produce the select bits, the distribution of addresses in a set of regular access patterns may be somewhat randomized to the channels/banks. In one implementation, each select bit may have a corresponding programmable bit vector that specifies the address bits to be included for that select bit. Accordingly, any subset of the address bits may be included in any select bit generation.
摘要翻译：在一个实施例中，存储器控制器可以被配置为在所选择的地址位上执行诸如散列函数的逻辑运算以产生通道或存储体选择的位。每个选择位的所选择的地址位可以不同，并且在一些实施例中可以是可编程的。通过组合所选择的地址位以产生选择位，一组常规访问模式中的地址分布可能随机化到信道/存储体。在一个实现中，每个选择位可以具有相应的可编程位向量，其指定要为该选择位包括的地址位。因此，地址位的任何子集可以被包括在任何选择位生成中。

40. 发明授权

US08055975B2 Combined single error correction/device kill detection code 有权
标题翻译：组合单错误纠正/设备杀死检测码
公开(公告)号：US08055975B2
公开(公告)日：2011-11-08
申请号：US11758322
申请日：2007-06-05
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

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