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31. 发明申请

US20080195993A1 Method of Generating Wiring Routes with Matching Delay in the Presence of Process Variation 有权
标题翻译：在过程变化存在下生成具有匹配延迟的接线路由的方法
公开(公告)号：US20080195993A1
公开(公告)日：2008-08-14
申请号：US12107158
申请日：2008-04-22
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

32. 发明授权

US07962874B2 Method and system for evaluating timing in an integrated circuit 有权
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07962874B2
公开(公告)日：2011-06-14
申请号：US12183549
申请日：2008-07-31
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

33. 发明授权

US07877714B2 System and method to optimize semiconductor power by integration of physical design timing and product performance measurements 有权
标题翻译：通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法
公开(公告)号：US07877714B2
公开(公告)日：2011-01-25
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译：提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。

34. 发明授权

US07865861B2 Method of generating wiring routes with matching delay in the presence of process variation 有权
标题翻译：在存在过程变化的情况下生成具有匹配延迟的布线路线的方法
公开(公告)号：US07865861B2
公开(公告)日：2011-01-04
申请号：US12107158
申请日：2008-04-22
申请人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.
摘要翻译：电路设计中的平衡延迟的方法和服务从通过布线设计连接在一起的节点开始，或通过提供要被改变的初始布线设计。布线设计将具有许多布线路径，例如第一布线路径，第二布线路径等。两条或多条布线路径被设计成具有匹配的定时，使得信号沿着第一布线路径行进所需的时间信号沿着第二布线路径，第三路径等移动所需的大致相同的时间。该方法/服务设计一个或所有布线路径，以使路径穿过大约相同长度的线段，并且在第一布线路径和第二布线路径横越的各布线层内。此外，该处理使得第一布线路径和第二布线路径在第一布线路径和第二布线路径横越的各布线层内以相同的顺序横穿线段。

35. 发明授权

US07489204B2 Method and structure for chip-level testing of wire delay independent of silicon delay 失效
标题翻译：线延迟芯片级测试的方法和结构独立于硅延迟
公开(公告)号：US07489204B2
公开(公告)日：2009-02-10
申请号：US11160603
申请日：2005-06-30
申请人： Peter A. Habitz , Anthony D. Polson
发明人： Peter A. Habitz , Anthony D. Polson
IPC分类号： G01R23/00 , H03B5/24 , H03K3/03
CPC分类号： G01R31/31725 , G01R31/3016
摘要： Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to either a first wire or a second wire by a multiplexer. A monitor measures ring frequencies of the ring oscillator when connected to either the first or second wire. A processor determines the wire delay based upon differences in the ring frequencies. Additional testers or multiple stages of a single tester may be embedded into either the same metal layer at a different location or into a different metal layer to allow for intra-metal layer or inter-metal layer comparisons of wire delay. Since metal capacitance and silicon load remains constant for both the first and second wires and the transient voltage change along the wire is hold small, metal delay is separable from delay due to silicon device performance. Pass/Fail criteria based upon a maximum allowable resistance-capacitance delay for a metal layer or based upon a comparison of resistance-capacitance delays across the same metal layer or between metal layers can be used to reject a chip.
摘要翻译：公开了用于在独立于硅延迟的芯片级测试位置特定的线延迟的方法和结构。本发明结合使用嵌入在芯片的金属层中的测试仪。测试器包括环形振荡器，其通过多路复用器选择性地连接到第一线或第二线。当连接到第一根或第二根导线时，监视器测量环形振荡器的振铃频率。处理器根据环频的差异来确定导线延迟。单个测试器的附加测试器或多个阶段可以嵌入到不同位置处的相同金属层中或者嵌入到不同的金属层中以允许金属间层或金属间层对比延迟线。由于金属电容和硅负载对于第一和第二导线都保持恒定，并且沿着导线的瞬态电压变化保持较小，所以由于硅器件性能，金属延迟与延迟分离。可以使用基于金属层的最大允许电阻 - 电容延迟或基于相同金属层或金属层之间的电阻 - 电容延迟的比较的通过/失败标准来拒绝芯片。

36. 发明申请

US20080216036A1 SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS 有权
公开(公告)号：US20080216036A1
公开(公告)日：2008-09-04
申请号：US12122451
申请日：2008-05-16
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Jeffrey H. Oppold , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5045
摘要： A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

37. 发明申请

US20080129330A1 Integrated Circuit Having State-Saving Input-Output Circuitry and a Method of Testing Such an Integrated Circuit 审中-公开
标题翻译：具有省电输入输出电路的集成电路和测试这种集成电路的方法
公开(公告)号：US20080129330A1
公开(公告)日：2008-06-05
申请号：US11566259
申请日：2006-12-04
申请人： Theodoros Anemikos , Michael R. Ouellette , Anthony D. Polson
发明人： Theodoros Anemikos , Michael R. Ouellette , Anthony D. Polson
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： G01R31/31713
摘要： An integrated circuit that includes input/output (I/O) state saving circuitry capable of stabilizing the I/O states during any predicted I/O disturbance event. The I/O state saving circuitry includes a plurality of transparent latches arranged between the output of a plurality of respective I/O receivers and the internal digital, analog, or mixed-signal circuitry of the integrated circuit. The transparent latches are transitioned between a pass-through mode and a state-saving mode via a common control signal. In anticipation of, for example, a predicted I/O signal disturbance generating event, the transparent latches are set to the state-saving mode. Consequently, the outputs of the transparent latches are held stable and glitchless during the disturbance event, which ensures that the internal logic of the integrated circuit does not lose state.
摘要翻译：一种集成电路，其包括能够在任何预测的I / O干扰事件期间稳定I / O状态的输入/输出（I / O）状态保存电路。 I / O状态保存电路包括布置在多个相应I / O接收器的输出端与集成电路的内部数字，模拟或混合信号电路之间的多个透明锁存器。透明锁存器通过公共控制信号在通过模式和状态保存模式之间转换。在预期的例如预测的I / O信号干扰发生事件中，透明锁存器被设置为状态保存模式。因此，在干扰事件期间，透明锁存器的输出保持稳定和无毛刺，这确保了集成电路的内部逻辑不会失去状态。

38. 发明授权

US07302673B2 Method and system for performing shapes correction of a multi-cell reticle photomask design 失效
标题翻译：用于执行多单元掩模版光掩模设计的形状校正的方法和系统
公开(公告)号：US07302673B2
公开(公告)日：2007-11-27
申请号：US11162586
申请日：2005-09-15
申请人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
发明人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

39. 发明授权

US07280939B2 System and method of analyzing timing effects of spatial distribution in circuits 有权
标题翻译：分析电路中空间分布的时序效应的系统和方法
公开(公告)号：US07280939B2
公开(公告)日：2007-10-09
申请号：US10709362
申请日：2004-04-29
申请人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G06F11/30 , G06F9/45
CPC分类号： G06F17/5031
摘要： Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.
摘要翻译：提供了系统和方法，用于通过考虑电路的路径或逻辑锥中的单元或元件的位置来分析电路的定时，包括集成电路。在一个实施例中，可以围绕感兴趣的细胞或元件限定边界区域，并且可以使用边界区域的大小来计算定时松弛变化因子。可以调整边界区域的大小以考虑定时延迟的变化。在其他实施例中，可以使用路径或锥体内的元件或单元的位置或延迟加权位置以及用于计算定时松弛变化因子的质心来计算质心。定时松弛变化因子用于计算电路的路径或逻辑锥的新的定时松弛。

40. 发明授权

US07089143B2 Method and system for evaluating timing in an integrated circuit 失效
标题翻译：用于评估集成电路中的定时的方法和系统
公开(公告)号：US07089143B2
公开(公告)日：2006-08-08
申请号：US10709361
申请日：2004-04-29
申请人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
发明人： Eric A. Foreman , Peter A. Habitz , David J. Hathaway , Jerry D. Hayes , Anthony D. Polson
IPC分类号： G01M19/00 , G06F9/45
CPC分类号： G01R31/3016
摘要： Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.
摘要翻译：用于分析集成电路中的定时并减少静态时序分析（STA）中定时松弛计算中的悲观情况的方法。该方法涉及分组和消除在早期和晚期电路路径中具有类似延迟的元件的延迟贡献。使用具有不同延迟的元件的延迟贡献来计算调整的定时松弛。在一些实施例中，具有不同延迟的元件的延迟贡献是根和平方。本发明的实施例提供了用于减少由于基于单元和线依赖的延迟引起的悲观的方法。在本发明的实施例中考虑的延迟可以包括由于路径中的元件的位置而导致的延迟。

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