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1. 发明授权

US07302673B2 Method and system for performing shapes correction of a multi-cell reticle photomask design 失效
标题翻译：用于执行多单元掩模版光掩模设计的形状校正的方法和系统
公开(公告)号：US07302673B2
公开(公告)日：2007-11-27
申请号：US11162586
申请日：2005-09-15
申请人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
发明人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

2. 发明授权

US06479974B2 Stacked voltage rails for low-voltage DC distribution 失效
标题翻译：用于低压直流分配的堆叠电压轨
公开(公告)号：US06479974B2
公开(公告)日：2002-11-12
申请号：US09750884
申请日：2000-12-28
申请人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
发明人： John Maxwell Cohn , Alvar Antonio Dean , David James Hathaway , Patrick Edward Perry , Sebastian Theodore Ventrone
IPC分类号： G05F304
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.
摘要翻译：一种用于提供片上电压分配和调节的系统和方法。根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

3. 发明授权

US07082065B2 Method and apparatus for efficient utilization of electronic fuse source connections 失效
标题翻译：电子熔断器源连接有效利用的方法和装置
公开(公告)号：US07082065B2
公开(公告)日：2006-07-25
申请号：US10711430
申请日：2004-09-17
申请人： David James Hathaway , Steven Joseph Urish
发明人： David James Hathaway , Steven Joseph Urish
IPC分类号： G11C29/00
CPC分类号： G06F17/5068
摘要： A method for and an apparatus in which the FSOURCE connection in a fuse domain is split into multiple nets, allowing flexible placement of primary fuses in the floorplan, is provided. In particular, multiple FSOURCE connections (e.g. C4 pads or wire pads) are provided in the floorplan, allowing flexible placement of primary fuses without additional overhead.
摘要翻译：提供了一种方法和一种设备，其中熔丝域中的FSOURCE连接被分成多个网络，允许在平面图中灵活地放置主熔丝。特别地，在平面布置图中提供了多个FSOURCE连接（例如，C4焊盘或焊盘），允许主熔丝的灵活放置而没有额外的开销。

4. 发明授权

US5757657A Adaptive incremental placement of circuits on VLSI chip 失效
标题翻译：电路在VLSI芯片上的自适应增量放置
公开(公告)号：US5757657A
公开(公告)日：1998-05-26
申请号：US597743
申请日：1996-02-07
申请人： David James Hathaway , John Maxwell Cohn
发明人： David James Hathaway , John Maxwell Cohn
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L27/04 , H01L21/98
CPC分类号： G06F17/5072
摘要： A computer implemented method incrementally updates a design placement in a very large scale integrated (VLSI) chip. A data structure is generated which defines a chosen specification and initial placement of circuits is input to a computer aided design (CAD) system. The CAD system divides a design area into placement cells. Local constraint values and limits are computed and changes made in the design specification. Replacement regions are then identified, expanded, and replaced. Constraint values are recomputed and the steps of the method are repeated until no more changes are required.
摘要翻译：计算机实现的方法逐步更新大规模集成（VLSI）芯片中的设计布局。生成数据结构，其定义了所选择的规范，并将电路的初始放置输入到计算机辅助设计（CAD）系统。 CAD系统将设计区域分为放置单元。计算局部约束值和限制，并在设计规范中进行更改。然后识别，扩展和替换替换区域。重新计算约束值，并重复该方法的步骤，直到不再需要更改为止。

5. 发明授权

US5740067A Method for clock skew cost calculation 失效
标题翻译：时钟偏移成本计算方法
公开(公告)号：US5740067A
公开(公告)日：1998-04-14
申请号：US547686
申请日：1995-10-19
申请人： David James Hathaway
发明人： David James Hathaway
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method of computing the cost of a proposed clock tree change in the context of a clock skew optimization routine. According to the present invention, a recalculation of the clock skew cost due to a proposed change in the clock tree can be done without having to recompute the effect of the change to all of the sinks of that clock tree. The method stores the effects of past delay changes as unpropagated incremental changes until future changes make it necessary to propagate those changes. Thus, in this method only the parameters of the ancestors of the delayed node need to be recalculated to determine the cost of a proposed change in the clock tree. Not having to recalculate the rest of the tree greatly reduces the computational complexity and time required for the process, allowing the required iterations to be completed in a much shorter time period.
摘要翻译：本发明提供了一种在时钟偏差优化例程的上下文中计算所提出的时钟树变化的成本的方法。根据本发明，可以进行由于时钟树中提出的改变引起的时钟偏移成本的重新计算，而不必重新计算对该时钟树的所有汇的变化的影响。该方法将过去的延迟更改的效果存储为未传播的增量更改，直到将来的更改使得有必要传播这些更改。因此，在该方法中，仅需要重新计算延迟节点的祖先的参数以确定时钟树中所提出的改变的成本。不必重新计算树的其余部分大大减少了该过程所需的计算复杂度和时间，从而允许在更短的时间内完成所需的迭代。

6. 发明授权

US06308302B1 Semiconductor wiring technique for reducing electromigration 失效
标题翻译：用于减少电迁移的半导体接线技术
公开(公告)号：US06308302B1
公开(公告)日：2001-10-23
申请号：US08944857
申请日：1997-10-06
申请人： David James Hathaway , Douglas Wayne Kemerer , William John Livingstone , Daniel Joseph Mainiero , Joseph Leonard Metz , Jeannie Therese Harrigan Panner
发明人： David James Hathaway , Douglas Wayne Kemerer , William John Livingstone , Daniel Joseph Mainiero , Joseph Leonard Metz , Jeannie Therese Harrigan Panner
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.
摘要翻译：一种具有至少一个源极引脚和多个引脚引脚的集成电路芯片。线段将源极引脚连接到至少一个引脚引脚，并且包括至少两个段，其中，其中一个段大于可能发生电迁移的其他段。

7. 发明授权

US06300809B1 Double-edge-triggered flip-flop providing two data transitions per clock cycle 有权
标题翻译：双边沿触发器，每个时钟周期提供两个数据转换
公开(公告)号：US06300809B1
公开(公告)日：2001-10-09
申请号：US09616551
申请日：2000-07-14
申请人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
发明人： Roger Paul Gregor , David James Hathaway , David E. Lackey , Steven Frederick Oakland
IPC分类号： H03K312
CPC分类号： H03K3/012 , H03K3/037 , H03K3/0375
摘要： An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
摘要翻译：一种包括用于提供时钟信号的时钟的装置，用于提供时钟信号的延迟版本的装置，具有由延迟的时钟信号的相反极性控制的时钟输入的两个透明锁存器，多路复用器具有（i）由锁存器和（ii）由时钟信号馈送的选择输入，以及用于提供用于选择时钟不活动的锁存器的选择信号的装置。优选地，每个锁存器具有扫描输入栅极和扫描输出栅极，并且第一锁存器的扫描输出被施加到第二锁存器的扫描输入以形成可扫描锁存器对。此外，优选地，该装置还包括用于将数据应用于第一和第二锁存器的数据端口和数据端口处的异或门，由此该装置产生门控时钟信号。还公开了一种操作该装置的方法。

8. 发明授权

US5745735A Localized simulated annealing 失效
标题翻译：局部模拟退火
公开(公告)号：US5745735A
公开(公告)日：1998-04-28
申请号：US549405
申请日：1995-10-26
申请人： John Maxwell Cohn , David James Hathaway
发明人： John Maxwell Cohn , David James Hathaway
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/505 , G06F17/5072 , Y10S706/92
摘要： According to the present invention, a method of optimization by simulated annealing is provided that uses a spatial metric to localize the simulated annealing temperature, the move set, and the objects which the moves operate on. The method keeps a local history of the optimization process. The localization allows the simulated annealing process to adaptively control the annealing schedule of each local region independently. This allows the annealing temperature, move set, and the objects upon which the move set operates to each be adjusted for each region independently to maximize efficiency. This results in optimization of all regions in a quick and efficient manner.
摘要翻译：根据本发明，提供了一种通过模拟退火优化的方法，其使用空间度量来定位模拟退火温度，移动集合以及移动操作的对象。该方法保留优化过程的本地历史。定位允许模拟退火过程独立地自适应地控制每个局部区域的退火时间表。这允许退火温度，移动设置以及移动组操作的对象各自独立地被调整以使效率最大化。这样可以快速有效地优化所有地区。

9. 发明授权

US07525373B1 Compensation of process and voltage variability in multi-threshold dynamic voltage scaling circuits 失效
标题翻译：多阈值动态电压缩放电路中过程和电压变化的补偿
公开(公告)号：US07525373B1
公开(公告)日：2009-04-28
申请号：US12123314
申请日：2008-05-19
申请人： Clarence Rosser Ogilvie , David Solomon Wolpert , David James Hathaway
发明人： Clarence Rosser Ogilvie , David Solomon Wolpert , David James Hathaway
IPC分类号： H01L25/00
CPC分类号： G06F17/5072 , G06F1/3203 , G06F1/3287 , G06F1/3296 , G06F2217/78 , G06F2217/84 , H01L27/0207 , Y02D10/171 , Y02D10/172
摘要： This invention relates to adaptively compensating for variations in integrated chip circuitry due to delays caused by multiple thresholds. The multi-threshold adaptive dynamic scaling system disclosed compensates for normal on-chip variations which affect system process and voltage variability, as well as overall performance. This system regulates a voltage control and provides high voltage thresholds, regular voltage thresholds, and low voltage thresholds to compensate for threshold voltage variations.
摘要翻译：本发明涉及由于多个阈值引起的延迟而自适应地补偿集成芯片电路的变化。所公开的多阈值自适应动态缩放系统补偿影响系统过程和电压变化以及整体性能的正常片上变化。该系统调节电压控制，并提供高电压阈值，常规电压阈值和低电压阈值以补偿阈值电压变化。

10. 发明授权

US06795951B2 Method and system for fault-tolerant static timing analysis 有权
标题翻译：容错静态时序分析方法与系统
公开(公告)号：US06795951B2
公开(公告)日：2004-09-21
申请号：US09780558
申请日：2001-02-09
申请人： David James Hathaway , Peter James Osler
发明人： David James Hathaway , Peter James Osler
IPC分类号： G08F1750
CPC分类号： G06F17/5031
摘要： A method and system for performing fault tolerant static timing analysis for an electronic network. A composite timing graph is generated by making K+1 copies of the zero-defect timing graph of the network, where K is a predetermined maximum number of defects present on a path of the network, and static timing analysis is performed on the composite timing graph.
摘要翻译：一种用于对电子网络执行容错静态时序分析的方法和系统。通过使网络的零缺陷时间图的K + 1个副本产生复合时序图，其中K是在网络的路径上存在的预定的最大数量的缺陷，并且对复合定时执行静态时序分析图形。

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