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1. 发明授权

US07302673B2 Method and system for performing shapes correction of a multi-cell reticle photomask design 失效
标题翻译：用于执行多单元掩模版光掩模设计的形状校正的方法和系统
公开(公告)号：US07302673B2
公开(公告)日：2007-11-27
申请号：US11162586
申请日：2005-09-15
申请人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
发明人： Peter Anton Habitz , David James Hathaway , Jerry D. Hayes , Anthony D. Polson , Tad Jeffrey Wilder
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.
摘要翻译：一种多光栅掩模版设计的掩模版设计校正和电参数提取的方法。该方法包括：选择多小区掩模版设计的小区设计的子集，小区设计子集的每个小区设计具有相应的处理形状，用于确定相应小区设计位置的小区设计子集的每个小区设计的相应形状; 基于每个相应形状的相应单元设计位置，确定每个单元设计的所有对应形状的共同形状处理规则; 以及仅对单元设计的子集的单个单元设计执行相应形状的形状处理，以生成用于所述单元设计的子集的结果数据。还有一种包括计算机可读程序代码的计算机可用介质，其具有适于实现掩模版设计校正和电提取的方法的算法。

2. 发明授权

US6023567A Method and apparatus for verifying timing rules for an integrated circuit design 失效
标题翻译：用于验证集成电路设计的时序规则的方法和装置
公开(公告)号：US6023567A
公开(公告)日：2000-02-08
申请号：US726589
申请日：1996-10-07
申请人： Peter James Osler , Tad Jeffrey Wilder , Charles Barry Winn
发明人： Peter James Osler , Tad Jeffrey Wilder , Charles Barry Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An automated process for timing rule verification for an integrated circuit design is disclosed. The process includes the step of checking the generated timing rules by comparing a given timing rule against a synthesized model to determine timing relationships in the model that are not included in the timing rule and timing relationships in the timing rule that are not present in the model.
摘要翻译：公开了用于集成电路设计的定时规则验证的自动化处理。该过程包括通过将给定的时序规则与合成模型进行比较来确定所产生的定时规则的步骤，以确定不包括在时序规则中的模型中的时序关系和不存在于模型中的定时规则中的定时关系。

3. 发明授权

US07480888B1 Design structure for facilitating engineering changes in integrated circuits 失效
标题翻译：集成电路工程变更的设计结构
公开(公告)号：US07480888B1
公开(公告)日：2009-01-20
申请号：US12124771
申请日：2008-05-21
申请人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
发明人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.
摘要翻译：在本发明的一个实施例中公开了体现在机器可读介质中的设计结构，包括用于促进在IC内的选定位置进行工程变更的灵活逻辑块。灵活的逻辑块具有一致且可识别的结构，使得可以使用简单的自动化过程来重新配置结构以执行不同的逻辑操作。在某些实施例中，柔性逻辑块包括具有多个输入和至少一个输出的电路，例如多路复用器。金属互连结构耦合到输入端，并且能够使用聚焦离子束（FIB）工具将每个输入端连接到几个电势之一。以这种方式，电路可以被配置为在硬件中存在IC中的部件之后执行不同的逻辑操作。

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