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31. 发明授权

US06756259B2 Gate insulating structure for power devices, and related manufacturing process 有权
标题翻译：功率器件门绝缘结构及相关制造工艺
公开(公告)号：US06756259B2
公开(公告)日：2004-06-29
申请号：US10061606
申请日：2002-02-01
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L218238
CPC分类号： H01L29/7802 , G11C29/14 , G11C29/50 , G11C2029/0403 , H01L21/76202 , H01L21/8238 , H01L29/6656 , H01L29/66712
摘要： Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.
摘要翻译：半导体功率器件包括第一导电类型的半导体层，其中形成包括第一导电类型的源极区的第二导电类型的体区，与半导体层重叠的栅极氧化层，主体区域，叠加到栅极氧化物层的多晶硅区域和叠加到多晶硅区域的第一绝缘材料的区域。该器件包括位于两个多晶硅区域和第一绝缘材料的区域的一侧上的第二绝缘材料的区域，以及位于主体区域上的开口附近的栅极氧化物层的区域，位于多晶硅区域之间的氧化物区域以及第二绝缘材料的区域，叠加到第二绝缘材料的区域的氧化物间隔物。

32. 发明授权

US5874338A MOS-technology power device and process of making same 失效
标题翻译： MOS技术功率器件及其制作工艺
公开(公告)号：US5874338A
公开(公告)日：1999-02-23
申请号：US493149
申请日：1995-06-21
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L29/739
CPC分类号： H01L29/66712 , H01L29/1095
摘要： A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. Ions of the first conductivity type are then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
摘要翻译：一种MOS技术的功率器件，包括具有设置在其中的体区的第一导电类型的半导体材料层。体区包括第二导电类型的重掺杂区域，第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域及其制造方法。制造半导体器件的方法包括在半导体材料层的表面的部分上形成绝缘栅极层，以使半导体材料层的选定部分露出。第二导电类型的离子注入到半导体材料层的选定区域中。注入的离子热扩散以形成体区，每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区，以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。然后将第一导电类型的离子注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。

33. 再颁专利

USRE35642E Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process 失效
标题翻译：集成高压双极功率晶体管和低压MOS功率晶体管结构在发射极开关配置和相关制造过程中
公开(公告)号：USRE35642E
公开(公告)日：1997-10-28
申请号：US447184
申请日：1995-05-22
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L27/07 , H01L29/76
CPC分类号： H01L27/0716
摘要： A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor on a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the tint, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.
摘要翻译：给出了发射极开关配置中的两个版本的集成结构的描述，其包括在低压MOS功率晶体管上的高压双极型功率晶体管。在垂直MOS版本中，双极晶体管的发射极区域完全被掩埋，部分地在第一N外延层中，部分地在第二N外延层中; MOS位于发射极区域的上方。因此，双极型是完全埋藏的主动结构。在水平MOS版本中，在N外延层中有两个P +区，构成双极晶体管基极的色调接收同一晶体管的N +发射极区; 第二个分别接收构成MOS源极和漏极区域的两个N +区域; 芯片的前部设有金属电镀，以确保MOS漏极和双极发射极触点之间的连接。

34. 发明授权

US09018635B2 Integrated electronic device with edge-termination structure and manufacturing method thereof 有权
标题翻译：具有边缘终端结构的集成电子装置及其制造方法
公开(公告)号：US09018635B2
公开(公告)日：2015-04-28
申请号：US13221778
申请日：2011-08-30
申请人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
发明人： Ferruccio Frisina , Angelo Magri' , Mario Giuseppe Saggio
IPC分类号： H01L29/16 , H01L29/78 , H01L29/267 , H01L29/06 , H01L29/10 , H01L29/40
CPC分类号： H01L29/66666 , H01L21/02529 , H01L21/02532 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/165 , H01L29/267 , H01L29/402 , H01L29/66431 , H01L29/7811 , H01L29/7813
摘要： An embodiment of an integrated electronic device formed in a semiconductor body delimited by a lateral surface, which includes: a substrate made of a first semiconductor material; a first epitaxial region made of a second semiconductor material, which overlies the substrate and defines a first surface; a second epitaxial region made of a third semiconductor material, which overlies the first surface and is in contact with the first epitaxial region, the third semiconductor material having a bandgap narrower than the bandgap of the second semiconductor material; an active area, extending within the second epitaxial region and housing at least one elementary electronic component; and an edge structure, arranged between the active area and the lateral surface, and including a dielectric region arranged laterally with respect to the second epitaxial region, which overlies the first surface and is in contact with the first epitaxial region.
摘要翻译：一种形成在由侧面限定的半导体主体中的集成电子器件的实施例，包括：由第一半导体材料制成的衬底; 由第二半导体材料制成的第一外延区，其覆盖在所述基板上并限定第一表面; 由第三半导体材料制成的第二外延区，其覆盖在第一表面上并与第一外延区接触，第三半导体材料具有比第二半导体材料的带隙窄的带隙; 有源区域，在所述第二外延区域内延伸并容纳至少一个基本电子部件; 以及边缘结构，其布置在所述有源区域和所述侧表面之间，并且包括相对于所述第二外延区域横向布置的介质区域，所述介电区域覆盖所述第一表面并与所述第一外延区域接触。

35. 发明授权

US06404010B2 MOS technology power device 有权
标题翻译： MOS技术电源设备
公开(公告)号：US06404010B2
公开(公告)日：2002-06-11
申请号：US09860809
申请日：2001-05-17
申请人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
发明人： Mario Saggio , Ferruccio Frisina , Angelo Magri'
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0615 , H01L29/0619 , H01L29/0634
摘要： A MOS technology power device is described which comprises a plurality of elementary active units and a part of said power device which is placed between zones where the elementary active units are formed. The part of the power device comprises at least two heavily doped body regions of a first conductivity type which are formed in a semiconductor layer of a second conductivity type, a first lightly doped semiconductor region of the first conductivity type which is placed laterally between the two body regions. The first semiconductor region is placed under a succession of a thick silicon oxide layer, a polysilicon layer and a metal layer. A plurality of second lightly doped semiconductor regions of the first conductivity type are placed under said at least two heavily doped body regions and under said first lightly doped semiconductor region of the first conductivity type, each region of said plurality of second lightly doped semiconductor regions of the first conductivity type being separated from the other by portions of said semiconductor layer of the second conductivity type.
摘要翻译：描述了MOS技术功率器件，其包括多个基本有源单元和放置在形成基本有源单元的区域之间的所述功率器件的一部分。功率器件的一部分包括形成在第二导电类型的半导体层中的第一导电类型的至少两个重掺杂体区域，第一导电类型的第一轻掺杂半导体区域横向放置在两者之间身体区域。第一半导体区域被放置在一连串厚的氧化硅层，多晶硅层和金属层之下。第一导电类型的多个第二轻掺杂半导体区域被放置在所述至少两个重掺杂体区域的下方，并且在所述第一导电类型的所述第一轻掺杂半导体区域的下方，所述多个第二轻掺杂半导体区域的每个区域所述第一导电类型通过所述第二导电类型的所述半导体层的一部分与另一个分离。

36. 发明授权

US5841167A MOS-technology power device integrated structure 失效
公开(公告)号：US5841167A
公开(公告)日：1998-11-24
申请号：US772657
申请日：1996-12-23
申请人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
发明人： Antonio Grimaldi , Antonino Schillaci , Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L21/336 , H01L23/482 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66712 , H01L23/4824 , H01L29/0696 , H01L29/1095 , H01L29/4238 , H01L29/7802 , H01L29/41725 , H01L2924/0002
摘要： A MOS-gated power device integrated structure comprises a plurality of elementary units formed in a semiconductor material layer of a first conductivity type. Each elementary unit is formed in a body stripe of a second conductivity type. There are a plurality of body stripes of the second conductivity type extending substantially in parallel to each other and at least one source region of the first conductivity type disposed within each body stripe. A conductive gate layer is insulatively disposed over the semiconductor material layer between the body stripes in the form of a first web structure. A second web structure of the second conductivity type is formed in the semiconductor material layer and comprises an annular frame portion surrounding the plurality of bodystripes and at least one first elongated stripe extending between two sides of the annular frame portion in a direction substantially orthogonal to the body stripes and that is merged at each end with the annular frame portion. The body stripes are divided by the at least one first elongated stripe into at least two groups of body stripes, wherein one end of each body stripe is merged with the annular frame portion of the second conductivity type and the other end is merged with the at least one first elongated stripe. A conductive gate finger is insulatively disposed above the first elongated stripe and is part of the first web structure. A conductive gate ring surrounds the conductive gate layer and the conductive gate finger and completes the first web structure. A metal gate finger is disposed above the conductive gate finger and is merged at its ends with a metal gate ring structure disposed above the conductive gate ring to provide a third web structure. Source metal plates cover the at least two groups of body stripes and contact each source region and each body stripe to form a source electrode of the power device. A bottom surface of the semiconductor material layer forms a drain of the power device.

37. 发明授权

US5817546A Process of making a MOS-technology power device 失效
标题翻译：制造MOS技术电源设备的过程
公开(公告)号：US5817546A
公开(公告)日：1998-10-06
申请号：US576989
申请日：1995-12-19
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L21/336 , H01L29/10 , H01L21/332
CPC分类号： H01L29/66712 , H01L29/1095 , Y10S148/126
摘要： A process forms a MOS-technology power device including a semiconductor material layer of a first conductivity type and a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type. The process includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. A dopant of the second conductivity type is implanted twice at different concentrations and energies into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. A dopant of the first conductivity type is then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
摘要翻译：一种工艺形成包括第一导电类型的半导体材料层和设置在其中的体区的MOS技术功率器件。身体区域包括第二导电类型的重掺杂区域，第二导电类型的轻掺杂区域和第一导电类型的重掺杂区域。该方法包括在半导体材料层的表面的部分上形成绝缘栅极层，以使半导体材料层的选定部分露出。将第二导电类型的掺杂剂以不同的浓度和能量注入到半导体材料层的选定区域中两次。注入的离子热扩散以形成体区，每个体区包括基本上与绝缘栅层的边缘对准的重掺杂区，以及通过第一掺杂剂在绝缘栅层下方的横向扩散形成的轻掺杂区。然后将第一导电类型的掺杂剂注入到重掺杂区域中以形成与绝缘栅极层的边缘基本对准的源极区域。

38. 发明授权

US5065213A Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process 失效
标题翻译：集成式高压双极型功率晶体管和低电压MOS功率晶体管结构在发光二极管开关配置和相关制造过程中
公开(公告)号：US5065213A
公开(公告)日：1991-11-12
申请号：US288405
申请日：1988-12-21
申请人： Ferruccio Frisina , Giuseppe Ferla
发明人： Ferruccio Frisina , Giuseppe Ferla
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07 , H01L29/739 , H01L29/78
CPC分类号： H01L27/0716 , Y10S148/009
摘要： A description is given of two versions of an integrated structure in the emitter switching configuration comprising a high-voltage bipolar power transistor an a low-voltage MOS power transistor. In the vertical MOS version, the emitter region of the bipolar transistor is completely buried, partly in a first N-epitaxial layer and partly in a second N epitaxial layer; the MOS is located above the emitter region. The bipolar is thus completely buried active sturcture. In the horizontal MOS version, in a N-epitaxial layer there are two P+regions, the first, which constitutes the base of the bipolar transistor, receives the N+emitter region of the same transistor; the second receives two N+regions which constitute the MOS source and drain regions, respectively; the front of the chip is provided with metal plating to ensure the connection between the MOS drain and the bipolar emitter contacts.

39. 发明申请

US20070102725A1 Insulated gate planar integrated power device with co-integrated Schottky diode and process 有权
标题翻译：具有共同集成肖特基二极管和工艺的绝缘栅平面集成功率器件
公开(公告)号：US20070102725A1
公开(公告)日：2007-05-10
申请号：US11520210
申请日：2006-09-12
申请人： Angelo Magri' , Ferruccio Frisina
发明人： Angelo Magri' , Ferruccio Frisina
IPC分类号： H01L29/74
CPC分类号： H01L29/66719 , H01L21/26586 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66712 , H01L29/66727 , H01L29/7806 , H01L29/7839 , H01L29/872
摘要： A process for integrating a Schottky contact inside the apertures of the elementary cells that constitute the integrated structure of the insulated gate power device in a totally self-alignment manner does not requires a dedicated masking step. This overcomes the limits to the possibility of increasing the packing density of the cellular structure of the integrated power device, while permitting improved performances of the co-integrated Schottky diode under inverse polarization of the device and producing other advantages. A planar integrated insulated gate power device with high packing density of the elementary cells that compose it, having a Schottky diode electrically in parallel to the co-integrated device, is also disclosed.
摘要翻译：以完全自对准的方式将构成绝缘栅功率器件的集成结构的单元的孔内的肖特基接触集成在一起的处理不需要专用的掩蔽步骤。这克服了增加集成功率器件的蜂窝结构的封装密度的可能性的限制，同时可以在器件的反极化下提高共同集成的肖特基二极管的性能并产生其他优点。还公开了一种平面集成绝缘栅功率器件，其具有构成该元件的单元的高封装密度，其具有与并联器件并联的肖特基二极管。

40. 发明授权

US06369425B1 High-density power device 失效
公开(公告)号：US06369425B1
公开(公告)日：2002-04-09
申请号：US08811363
申请日：1997-03-06
申请人： Giuseppe Ferla , Ferruccio Frisina
发明人： Giuseppe Ferla , Ferruccio Frisina
IPC分类号： H01L2976
CPC分类号： H01L29/66719 , H01L21/26586 , H01L29/0696 , H01L29/1095 , H01L29/66712 , Y10S148/126
摘要： A process for manufacturing high-density MOS-technology power devices includes the steps of: forming a conductive insulated gate layer on a surface of a lightly doped semiconductor material layer of a first conductivity type; forming an insulating material layer over the insulated gate layer; selectively removing the insulating material layer and the underlying insulated gate layer to form a plurality of elongated windows having two elongated edges and two short edges, delimiting respective uncovered surface stripes of the semiconductor material layer; implanting a high dose of a first dopant of the first conductivity type along two directions which lie in a plane transversal to said elongated windows and orthogonal to the semiconductor material layer surface, and which are substantially symmetrically tilted at a first prescribed angle with respect to a direction orthogonal to the semiconductor material layer surface, the first angle depending on the overall thickness of the insulated gate layer and of the insulating material layer to prevent the first dopant from being implanted in a central stripe of said uncovered surface stripes, to form pairs of heavily doped elongated source regions of the first conductivity type which extend along said two elongated edges of each elongated window and which are separated by said central stripe; implanting a low dose of a second dopant of a second conductivity type along two directions which lie in said plane, and which are substantially symmetrically tilted of a second prescribed angle with respect to said orthogonal direction, to form doped regions of the second conductivity type each comprising two lightly doped elongated channel regions extending under the two elongated edges of each elongated window; implanting a high dose of a third dopant of the second conductivity type substantially along said orthogonal direction, the insulating material layer acting as a mask, to form heavily doped regions substantially aligned with the edges of the elongated windows.

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