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31. 发明授权

US08427229B2 Integrated circuits with bi-directional charge pumps 有权
标题翻译：具有双向电荷泵的集成电路
公开(公告)号：US08427229B2
公开(公告)日：2013-04-23
申请号：US13038519
申请日：2011-03-02
申请人： Yvonne Lin , Tien-Chun Yang
发明人： Yvonne Lin , Tien-Chun Yang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/02 , G11C5/145 , H02M3/07
摘要： Integrated circuits such as memory arrays are coupled to a bi-directional charge pump that includes an input circuit and output circuit, and one or more pump stages coupled between the input circuit and the output circuit of the bi-directional charge pump. The output circuit includes a diode having an input and output and a transistor connected to the output of the diode and a ground potential. The input of the diode is electrically connected to the pump stages in a configuration that allows the charge pump to apply a positive or negative voltage to the memory array or other load.
摘要翻译：诸如存储器阵列的集成电路耦合到双向电荷泵，其包括输入电路和输出电路，以及耦合在双向电荷泵的输入电路和输出电路之间的一个或多个泵级。输出电路包括具有输入和输出的二极管和连接到二极管的输出和地电位的晶体管。二极管的输入以允许电荷泵将正或负电压施加到存储器阵列或其它负载的配置电连接到泵级。

32. 发明授权

US07505298B2 Transfer of non-associated information on flash memory devices 有权
标题翻译：在闪存设备上传送非相关信息
公开(公告)号：US07505298B2
公开(公告)日：2009-03-17
申请号：US11741996
申请日：2007-04-30
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C8/12 , G11C7/12 , G11C7/18 , G11C16/24 , G11C2207/002
摘要： Manners for transferring information within a flash memory device across a memory array are described. A controller retrieves information from a storage unit and then a decoder decodes the information. The information is set across a series of bitlines through a pass gate to a second controller. The bitlines are both associated with the storage unit as well as bitlines associated with other storage units. A series of transistors is associated with each bitline. Different transistors are active based on if the bitlines are associated with the currently used storage unit.
摘要翻译：描述了通过存储器阵列在闪速存储器件内传送信息的方式。控制器从存储单元检索信息，然后解码器解码该信息。信息通过一个通过门到一个第二个控制器的一系列位线设置。位线都与存储单元相关联，以及与其他存储单元相关联的位线。一系列晶体管与每个位线相关联。基于如果位线与当前使用的存储单元相关联，不同的晶体管是有效的。

33. 发明申请

US20080136381A1 Method to provide a higher reference voltage at a lower power supply in flash memory devices 有权
标题翻译：在闪存器件中的较低电源处提供较高参考电压的方法
公开(公告)号：US20080136381A1
公开(公告)日：2008-06-12
申请号：US11634776
申请日：2006-12-06
申请人： Tien-Chun Yang , Yonggang Wu , Nian Yang
发明人： Tien-Chun Yang , Yonggang Wu , Nian Yang
IPC分类号： G05F1/10 , G11C5/14
CPC分类号： G11C5/147 , G05F3/08 , G11C16/30
摘要： A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith. The comparator circuit is configured to compare the bias supply voltage to the reference voltage, and drive the bias supply and the variable divider circuit in response to the comparison, thereby quickly stabilizing the reference voltage.
摘要翻译：具有有源反馈的快速参考电路包括偏置电源电路和通过有源反馈路径连接到偏置电源电路的可变分频器电路，以及连接到可变分频器电路，偏置电源电路和参考节点的参考节点可变分频电路。在一个实施例中，启动电路首先在偏置电源和比较器电路处放电，然后在约零伏特的参考节点初始化参考电压，以提高可重复性。在一个实施例中，可变分压器包括基于用于制造快速参考电路的工艺的薄层电阻而修整的阻抗，并且还包括耦合到阻抗的可变参考电流电路，并且被配置为产生具有基于所需参考电压的值，并且将电流传导通过阻抗，由此产生与其相关联的参考电压。比较器电路被配置为将偏置电源电压与参考电压进行比较，并且响应于比较来驱动偏置电源和可变分频器电路，由此快速稳定参考电压。

34. 发明授权

US07142454B2 System and method for Y-decoding in a flash memory device 有权
标题翻译：闪存设备中Y解码的系统和方法
公开(公告)号：US07142454B2
公开(公告)日：2006-11-28
申请号：US10243315
申请日：2002-09-12
申请人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
发明人： Tien-Chun Yang , Ming-Huei Shieh , Kurihara Kazuhiro , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0458 , G11C16/0475 , G11C16/0491
摘要： A system and method for column selection in a non-volatile memory cell array is disclosed. A group of memory cells is arranged in a rectangular array having rows (X-dimension) and columns (Y-dimension). Within a row, the sources and drains of the memory cells are connected to form a linear chain. A common word line is coupled to each gate in the row. A separate column line is coupled to each node between adjacent memory cells of the chain. A four column Y-decoder is used to select column lines for sense operations. A voltage source is applied to two of the four column lines during the sense operation. Current on one of the column lines may be sensed to provide a measurement for read or verification.
摘要翻译：公开了一种用于非易失性存储单元阵列中的列选择的系统和方法。一组存储单元被布置成具有行（X维）和列（Y维）的矩形阵列。在一行中，存储器单元的源极和漏极被连接以形成线性链。公共字线连接到行中的每个门。单独的列线耦合到链的相邻存储器单元之间的每个节点。四列Y解码器用于选择用于感测操作的列线。在感测操作期间，将电压源施加到四列中的两条线。可以感测一列列线上的电流以提供用于读取或验证的测量。

35. 发明授权

US06859393B1 Ground structure for page read and page write for flash memory 有权
标题翻译： Flash存储器的页面读取和页面写入的接地结构
公开(公告)号：US06859393B1
公开(公告)日：2005-02-22
申请号：US10264387
申请日：2002-10-04
申请人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
发明人： Tien-Chun Yang , Shigekazu Yamada , Ming-Huei Shieh , Pau-Ling Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , G11C2216/14
摘要： A ground structure for page read and page write for flash memory. An array structure of flash memory cells comprises a plurality of sectors. Each sector comprises I/O blocks plus reference arrays and an array of redundant cells. Each I/O block comprises sub I/O blocks. Each sub I/O block within an I/O block, as well as other structures including reference cells, redundant cells and edge structures is coupled to a unique ground reference signal. These unique ground reference signals may be selectively coupled to a system ground or a biased ground reference. This novel ground arrangement enables a page read operation in which one bit from each sub I/O block can be read simultaneously. In addition, one bit from each I/O block may be programmed simultaneously. Further, the ground reference voltage for cells of the array may be selectively adjusted to optimize operation.
摘要翻译：用于闪存的页面读取和页面写入的接地结构。闪存单元的阵列结构包括多个扇区。每个扇区包括I / O块加参考阵列和冗余单元阵列。每个I / O块包括子I / O块。 I / O块内的每个子I / O块以及包括参考单元，冗余单元和边缘结构的其他结构都耦合到独特的接地参考信号。这些独特的接地参考信号可以选择性地耦合到系统接地或偏置的接地参考。这种新颖的接地布置使得能够同时读取来自每个子I / O块的一个位的页面读取操作。另外，每个I / O块的一位可以同时编程。此外，可以选择性地调整阵列的单元的接地参考电压以优化操作。

36. 发明授权

US06728160B1 Path gate driver circuit 有权
标题翻译：路径驱动电路
公开(公告)号：US06728160B1
公开(公告)日：2004-04-27
申请号：US10243433
申请日：2002-09-12
申请人： Tien-Chun Yang , Kurihara Kazuhiro , Pau-Ling Chen
发明人： Tien-Chun Yang , Kurihara Kazuhiro , Pau-Ling Chen
IPC分类号： G11C800
CPC分类号： G11C16/24 , G11C7/1051 , G11C7/12
摘要： A path gate driver circuit of the present invention includes a shunt stage, a level shifter stage, a pull-up stage, and an output stage. The shunt stage has a control terminal coupled to a supply, and an input terminal coupled to a control signal path. The level shifter stage has a first control terminal coupled to the control signal path, a second control terminal coupled to an output terminal of the shunt stage, a first input terminal coupled to a boost-low supply, and a second input terminal coupled to a boost-high supply. The pull-up stage has a control terminal coupled to an output terminal of the level shifter stage, and an input terminal coupled to the boost-high supply. The output stage has a first control terminal coupled to the output terminal of the shunt stage and an output terminal of the pull-up stage, a second control terminal coupled to the control signal path a first input terminal coupled to the boost-low supply, and a second input terminal coupled to the boost-high supply. A boosted control signal is provided at the output terminal of the output stage in response to the control.
摘要翻译：本发明的路径栅极驱动电路包括分路级，电平转换级，上拉级和输出级。分流级具有耦合到电源的控制端子和耦合到控制信号路径的输入端子。电平移位器级具有耦合到控制信号路径的第一控制端，耦合到并联级的输出端的第二控制端，耦合到升压低电源的第一输入端和耦合到增加高的供应。上拉级具有耦合到电平移位器级的输出端子的控制端子和耦合到升压高电源的输入端子。输出级具有耦合到并联级的输出端和上拉级的输出端的第一控制端，耦合到控制信号路径的第二控制端，耦合到升压低电源的第一输入端，以及耦合到所述升压高电源的第二输入端子。响应于该控制，在输出级的输出端提供升压控制信号。

37. 发明申请

US20100215139A1 COUNTERS AND EXEMPLARY APPLICATIONS 有权
标题翻译：计数器和示例应用程序
公开(公告)号：US20100215139A1
公开(公告)日：2010-08-26
申请号：US12699458
申请日：2010-02-03
申请人： Chih-Chang LIN , Tien-Chun Yang , Steven Swei
发明人： Chih-Chang LIN , Tien-Chun Yang , Steven Swei
IPC分类号： H03K23/00
CPC分类号： H03K21/38
摘要： Embodiments described herein are related to a counter. In some embodiments, the counter can be used as a divider, e.g., in a fractional PLL. In some embodiments, the counter (e.g., the main counter or counter C) includes a first counter (e.g., counter C1) and a second counter (e.g., counter C2), which, together with the first counter C1, perform the counting function for counter C. For example, if counter C is to count to the value N, then counter C1 counts, e.g., to N1, and counter C2 counts to N2 where N=N1+N2. For counter C1 to count to N1, N1 is loaded to counter C1. Similarly, for counter C2 to count to N2, N2 is loaded to counter C2. While counter C1 counts (e.g., to N1), N2 can be loaded to counter C2. After counter C1 finishes counting to N1, N2, if loaded, is available for counter C2 to start counting to this N2. Counters C1 and C2 can alternately count and thus provide continuous counting for counter C. Other embodiments and exemplary applications are also disclosed.
摘要翻译：本文描述的实施例涉及计数器。在一些实施例中，计数器可以用作分频器，例如在分数PLL中。在一些实施例中，计数器（例如，主计数器或计数器C）包括第一计数器（例如，计数器C1）和第二计数器（例如，计数器C2），其与第一计数器C1一起执行计数功能对于计数器C.例如，如果计数器C计数到值N，则计数器C1计数，例如，到N1，并且计数器C2计数到N2，其中N = N1 + N2。对于计数器C1计数到N1，N1被加载到计数器C1。类似地，对于计数器C2计数到N2，N2被加载到计数器C2。当计数器C1计数（例如，到N1）时，可以将N2加载到计数器C2。在计数器C1结束计数到N1之后，N2（如果加载）可用于计数器C2开始计数到这个N2。计数器C1和C2可以交替地计数并因此为计数器C提供连续计数。还公开了其他实施例和示例性应用。

38. 发明授权

US07746706B2 Methods and systems for memory devices 有权
标题翻译：存储器件的方法和系统
公开(公告)号：US07746706B2
公开(公告)日：2010-06-29
申请号：US11639935
申请日：2006-12-15
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C16/04
CPC分类号： G11C16/3404 , G11C16/0475
摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及访问存储器单元的方法。在该方法中，擦除存储单元的至少一位。在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。还公开了其它方法和系统。

39. 发明申请

US20080144391A1 Methods and systems for memory devices 有权
标题翻译：存储器件的方法和系统
公开(公告)号：US20080144391A1
公开(公告)日：2008-06-19
申请号：US11639935
申请日：2006-12-15
申请人： Nian Yang , Yonggang Wu , Tien-Chun Yang
发明人： Nian Yang , Yonggang Wu , Tien-Chun Yang
IPC分类号： G11C16/10
CPC分类号： G11C16/3404 , G11C16/0475
摘要： One embodiment of the invention relates to a method for accessing a memory cell. In this method, at least one bit of the memory cell is erased. After erasing the at least one bit, a soft program operation is performed to bias the memory cell thereby improving the reliability of data stored in the memory cell.Other methods and systems are also disclosed.
摘要翻译：本发明的一个实施例涉及访问存储器单元的方法。在该方法中，擦除存储单元的至少一位。在擦除至少一个位之后，执行软编程操作以偏置存储器单元，从而提高存储在存储单元中的数据的可靠性。还公开了其它方法和系统。

40. 发明授权

US06944057B1 Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference 有权
标题翻译：使用温度依赖电压参考获得温度独立程序阈值电压分布的方法
公开(公告)号：US06944057B1
公开(公告)日：2005-09-13
申请号：US10431065
申请日：2003-05-06
申请人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
发明人： Edward F. Runnion , Tien-Chun Yang , Binh Quang Le , Shigekazu Yamada , Darlene G. Hamilton , Ming-Huei Shieh , Pau-Ling Chen , Kazuhiro Kurihara
IPC分类号： G11C16/06
CPC分类号： G11C16/3418 , G11C16/10
摘要： A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.
摘要翻译：描述了一种用于控制存储器件中的栅极电压的方法。该方法包括提供适于与存储器件耦合的电路。该电路用于产生参考电压。该方法还包括利用由电路提供的参考电压来在存储器件的栅极处施加电压。电压具有对应于存储器件的温度的值。该方法还包括保持参考电压与存储器件的温度之间的比例关系，而与存储器件的温度变化无关。参考电压为存储器件提供基本上恒定的编程时间，而与存储器件的温度无关。

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