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31. 发明授权

US6063711A High selectivity etching stop layer for damascene process 失效
标题翻译：用于镶嵌工艺的高选择性蚀刻停止层
公开(公告)号：US6063711A
公开(公告)日：2000-05-16
申请号：US69456
申请日：1998-04-28
申请人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
发明人： Li-Chih Chao , Chia-Shiung Tsai , Chu-Yun Fu , Jhon-Jhy Liaw
IPC分类号： H01L21/768 , H01L21/304 , B24B1/00 , H01L21/461
CPC分类号： H01L21/7681 , H01L21/76807
摘要： A high selectivity etch-stop layer comprising oxynitride is disclosed for forming damascene structures in the manufacturing of semiconductor substrates. Because of its relatively high selectivity to oxides, the oxynitride etch-stop can be made thinner than the conventionally used nitride layer. Therefore, the disclosed oxynitride etch-stop layer makes it possible to avoid the cracking problems of thicker etch-stop layers as well as the associated problems of poor definition of contact or via holes in the damascene structure.
摘要翻译：公开了一种包括氮氧化物的高选择性蚀刻停止层，用于在半导体衬底的制造中形成镶嵌结构。由于氧化物的选择性相对较高，氧氮化物蚀刻停止可以比常规使用的氮化物层薄。因此，所公开的氧氮化物蚀刻停止层使得可以避免较厚的蚀刻停止层的破裂问题以及相似的在镶嵌结构中接触或通孔的定义不良的问题。

32. 发明授权

US08580653B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08580653B2
公开(公告)日：2013-11-12
申请号：US13775907
申请日：2013-02-25
申请人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
发明人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
摘要翻译：一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物该方法还包括在第一氧化物的顶部产生固体反应产物。该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。该方法还包括用第二氧化物填充沟槽。

33. 发明授权

US07119404B2 High performance strained channel MOSFETs by coupled stress effects 有权
标题翻译：高性能应变通道MOSFET通过耦合应力效应
公开(公告)号：US07119404B2
公开(公告)日：2006-10-10
申请号：US10849689
申请日：2004-05-19
申请人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
发明人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
IPC分类号： H01L31/62 , H01L21/8238
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
摘要翻译：包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。

34. 发明授权

US07098116B2 Shallow trench isolation method for reducing oxide thickness variations at different pattern densities 有权
标题翻译：浅沟槽隔离方法可减少不同图案密度下的氧化物厚度变化
公开(公告)号：US07098116B2
公开(公告)日：2006-08-29
申请号：US10753816
申请日：2004-01-08
申请人： Chih-Cheng Lu , Chuan-Ping Hou , Chu-Yun Fu , Chang Wen , Jang Syun Ming
发明人： Chih-Cheng Lu , Chuan-Ping Hou , Chu-Yun Fu , Chang Wen , Jang Syun Ming
IPC分类号： H01L21/76
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31053 , H01L21/31055 , H01L21/31116 , H01L21/31612 , H01L21/76229
摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.
摘要翻译：描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻，以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。

35. 发明申请

US20060024879A1 Selectively strained MOSFETs to improve drive current 审中-公开
标题翻译：选择性应变MOSFET来提高驱动电流
公开(公告)号：US20060024879A1
公开(公告)日：2006-02-02
申请号：US10902973
申请日：2004-07-31
申请人： Chu-Yun Fu , Cheng-Hung Chang
发明人： Chu-Yun Fu , Cheng-Hung Chang
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/0214 , H01L21/0217 , H01L21/02274 , H01L21/3185 , H01L21/823807 , H01L29/7842 , H01L29/7843
摘要： A MOSFET device pair with improved drive current and a method for producing the same to selectively introduce strain into a respective N-type and P-type MOSFET device channel region, the method including forming a compressive stressed nitride layer on over the P-type MOSFET device and a tensile stressed nitride layer on the N-type MOSFET device followed by forming a PMD layer having a less compressive or tensile stress.
摘要翻译：一种具有改进的驱动电流的MOSFET器件对及其制造方法，用于选择性地将应变引入相应的N型和P型MOSFET器件沟道区，该方法包括在P型MOSFET上形成压应力氮化物层器件和N型MOSFET器件上的拉伸应力氮化物层，随后形成具有较小压缩或拉伸应力的PMD层。

36. 发明申请

US20050153519A1 Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities 有权
标题翻译：用于减小不同图案密度下氧化物厚度变化的新型浅沟槽隔离方法
公开(公告)号：US20050153519A1
公开(公告)日：2005-07-14
申请号：US10753816
申请日：2004-01-08
申请人： Chih-Cheng Lu , Chuan-Ping Hou , Chu-Yun Fu , Chang Wen , Jang Ming
发明人： Chih-Cheng Lu , Chuan-Ping Hou , Chu-Yun Fu , Chang Wen , Jang Ming
IPC分类号： H01L21/3105 , H01L21/311 , H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/02304 , H01L21/31053 , H01L21/31055 , H01L21/31116 , H01L21/31612 , H01L21/76229
摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.
摘要翻译：描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻，以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。

37. 发明授权

US06713406B1 Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices 失效
标题翻译：通过HDP（高密度等离子体）CVD（化学气相沉积）方法将电介质材料沉积到半导体衬底上而不损害FET有源器件的方法
公开(公告)号：US06713406B1
公开(公告)日：2004-03-30
申请号：US09809833
申请日：2001-03-19
申请人： Chu-Yun Fu , Kuo-Chyuan Tzeng
发明人： Chu-Yun Fu , Kuo-Chyuan Tzeng
IPC分类号： H01L21302
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02164 , H01L21/3105 , H01L21/31612 , H01L21/31625
摘要： Improved processes for depositing dielectric layers by HDP (High Density Plasma) CVD (Chemical Vapor Deposition) are described. One method controls the RF power applied to the side source RF power to be less than about 2500 Watts during dielectric deposition. A second method controls the thickness of the HDP-CVD deposited dielectric layer to be less than between about 2000 and 3000 Angstroms. These methods of HDP-CVD deposition of dielectric layers result in elimination or suppression of plasma induced damage to MOSFET devices and improved gate oxide integrity of MOSFET devices following deposition of dielectric layers by HDP-CVD.
摘要翻译：描述了通过HDP（高密度等离子体）CVD（化学气相沉积）沉积电介质层的改进方法。在电介质沉积期间，一种方法控制施加到侧源RF功率的RF功率小于约2500瓦。第二种方法控制HDP-CVD沉积介电层的厚度小于约2000和3000埃之间。介电层的HDP-CVD沉积的这些方法导致在通过HDP-CVD沉积介电层之后消除或抑制对MOSFET器件的等离子体诱导的损坏并改善MOSFET器件的栅极氧化物完整性。

38. 发明授权

US06479385B1 Interlevel dielectric composite layer for insulation of polysilicon and metal structures 有权
标题翻译：用于多晶硅和金属结构绝缘的层间电介质复合层
公开(公告)号：US06479385B1
公开(公告)日：2002-11-12
申请号：US09583397
申请日：2000-05-31
申请人： Syun-Ming Jang , Chu-Yun Fu
发明人： Syun-Ming Jang , Chu-Yun Fu
IPC分类号： H01L21302
CPC分类号： H01L21/02238 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02255 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/31625 , H01L21/76801 , H01L21/76837
摘要： A process for forming a composite, interlevel dielectric, (ILD), layer, for MOSFET devices, has been developed. The composite ILD layer is comprised with an underlying, undoped silicon glass layer, providing the material needed to fill the narrow spaces between polysilicon gate structures of the MOSFET devices. A P2O5 doped, insulator layer, is next formed on the underlying, undoped silicon glass layer, to provide a mobile ion gettering property. An overlying, undoped silicon glass layer is then deposited and subjected to a chemical mechanical polishing procedure, resulting in the desired planar top surface topography, for the composite ILD layer.
摘要翻译：已经开发了用于形成MOSFET器件的复合层间电介质（ILD）层的工艺。复合ILD层包含底层的未掺杂的硅玻璃层，提供填充MOSFET器件的多晶硅栅极结构之间的狭窄空间所需的材料。随后在下面未掺杂的硅玻璃层上形成P2O5掺杂的绝缘体层，以提供移动离子吸杂性质。然后沉积覆盖的未掺杂的硅玻璃层，并进行化学机械抛光程序，得到复合ILD层所需的平面顶表面形貌。

39. 发明授权

US06245682B1 Removal of SiON ARC film after poly photo and etch 有权
标题翻译：在多晶和蚀刻后去除SiON ARC膜
公开(公告)号：US06245682B1
公开(公告)日：2001-06-12
申请号：US09266374
申请日：1999-03-11
申请人： Chu-Yun Fu , Syun-Ming Jang
发明人： Chu-Yun Fu , Syun-Ming Jang
IPC分类号： H01L21311
CPC分类号： H01L21/32139 , H01L21/28123 , H01L21/31111 , H01L21/3145 , Y10S438/952
摘要： This invention relates to the fabrication of integrated circuit devices and more particularly to a method for forming and then later removing a silicon oxynitride, SiON, anti-reflection coating (ARC) over a semiconductor substrate, for the purpose of enhancing the resolution of photolithographically defined sub-micron polysilicon gates. The problem addressed by this invention is that the SiON ARC must first be used to reduce optical reflection from a blanket polysilicon surface, during the photolithography exposure step that defines the sub-micron polysilicon gate features, and then the ARC must be removed by a wet etch process that will not chemically attack the gate oxide under the polysilicon gate features or any exposed polysilicon surfaces. This is accomplished with a fabrication method that uses hot phosphoric acid (H3PO4) to preferentially etch the SiON ARC, relative to the thermal gate oxide, while also using thin thermal oxide layers to protect the polysilicon gate surfaces from being severely attacked by the hot H3PO4. This new method also features the ability to tailor the combination of the composition and thickness of the SiON layer and the thickness of the underlying protective thin thermal oxide layer, in order to minimize the undesired high optical reflectivity of the underlying polysilicon surface.
摘要翻译：本发明涉及集成电路器件的制造，更具体地说，涉及一种用于在半导体衬底上形成并随后去除氧氮化硅SiON，抗反射涂层（ARC）的方法，用于增强光刻定义的分辨率亚微米多晶硅门。本发明解决的问题是，在限定亚微米多晶硅栅极特征的光刻曝光步骤期间，必须首先使用SiON ARC来减少来自覆盖多晶硅表面的光学反射，然后必须通过湿法去除ARC 不会在多晶硅栅极特征或任何暴露的多晶硅表面下化学侵蚀栅极氧化物的蚀刻工艺。这是通过使用热磷酸（H 3 PO 4）相对于热栅氧化物优先蚀刻SiON ARC的制造方法实现的，同时还使用薄的热氧化物层来保护多晶硅栅极表面免受热H3PO4的严重攻击。这种新方法还具有能够定制SiON层的组成和厚度以及下面的保护性薄热氧化物层的厚度的组合，以便使底层多晶硅表面的不期望的高光学反射率最小化。

40. 发明授权

US06207483B1 Method for smoothing polysilicon gate structures in CMOS devices 有权
标题翻译： CMOS器件中多晶硅栅极结构平滑化的方法
公开(公告)号：US06207483B1
公开(公告)日：2001-03-27
申请号：US09527183
申请日：2000-03-17
申请人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
发明人： Chu-Yun Fu , Chung-Long Chang , Syun-Ming Jang , Shwangming Jeng
IPC分类号： H01L218238
CPC分类号： H01L21/823828 , H01L21/28035 , H01L21/32115
摘要： There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.
摘要翻译：提供了一种用于平滑CMOS结构的未掺杂多晶硅区域的表面的方法，主要是栅极区域。使用直接HPD-CVD氩溅射将表面粗糙度提高了50％以上。氩等离子体溅射可以单独使用或与氧化物，氮化物或氮氧化物的薄覆盖层结合使用。与使用常规制造工艺制造的器件相比，使用该工艺制造的器件表现出优异的电气特性和改进的可靠性。

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