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31. 发明授权

US06420250B1 Methods of forming portions of transistor structures, methods of forming array peripheral circuitry, and structures comprising transistor gates 有权
标题翻译：形成晶体管结构部分的方法，形成阵列外围电路的方法以及包括晶体管栅极的结构
公开(公告)号：US06420250B1
公开(公告)日：2002-07-16
申请号：US09518508
申请日：2000-03-03
申请人： Chih-Chen Cho , Richard H. Lane , Charles H. Dennison
发明人： Chih-Chen Cho , Richard H. Lane , Charles H. Dennison
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28247 , H01L21/76829 , H01L21/823425 , H01L21/823468 , H01L27/10894
摘要： The invention encompasses a method of forming a portion of a transistor structure. A substrate is provided, and a transistor gate is formed over the substrate. The transistor gate has a sidewall. A silicon oxide is deposited over a portion of the substrate proximate the transistor gate by high density plasma deposition. A spacer is formed over the silicon oxide and along the sidewall of the transistor gate. The invention also encompasses a method of oxidizing a portion of a conductive structure. Additionally, the invention encompasses transistor gate structures, as well as structures comprising memory array and peripheral circuitry.
摘要翻译：本发明包括形成晶体管结构的一部分的方法。提供衬底，并且在衬底上形成晶体管栅极。晶体管栅极具有侧壁。通过高密度等离子体沉积，氧化硅沉积在靠近晶体管栅极的衬底的一部分上。在氧化硅上并沿着晶体管栅极的侧壁形成间隔物。本发明还包括氧化导电结构的一部分的方法。另外，本发明包括晶体管栅极结构以及包括存储器阵列和外围电路的结构。

32. 发明授权

US06414392B1 Integrated circuit contact 有权
标题翻译：集成电路接触
公开(公告)号：US06414392B1
公开(公告)日：2002-07-02
申请号：US09569578
申请日：2000-05-10
申请人： Charles H. Dennison , Trung T. Doan
发明人： Charles H. Dennison , Trung T. Doan
IPC分类号： H01L2348
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76808 , H01L21/76829 , Y10S438/95 , Y10S438/97
摘要： A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multi-level metal integrated circuits.
摘要翻译：在集成电路的制造中形成垂直触点的工艺以及如此制造的器件。该过程消除了对精确掩模对准的需要，并允许独立于互连槽的蚀刻来控制接触孔的蚀刻。该方法包括以下步骤：在衬底的表面上形成绝缘层; 在绝缘层的表面上形成蚀刻停止层; 在蚀刻停止层中形成开口; 蚀刻到穿过蚀刻停止层中的开口的第一深度并进入绝缘层以形成互连槽; 在蚀刻停止层和槽中的表面上形成光致抗蚀剂掩模; 并且继续蚀刻通过绝缘层直到到达衬底的表面以形成接触孔。在形成多级金属集成电路期间，可以重复上述过程一次或多次。

33. 发明授权

US06410951B1 Structure for improving static refresh 有权
公开(公告)号：US06410951B1
公开(公告)日：2002-06-25
申请号：US09822249
申请日：2001-04-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L21336
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.

34. 发明授权

US06406977B2 Isolation region forming methods 失效
标题翻译：隔离区形成方法
公开(公告)号：US06406977B2
公开(公告)日：2002-06-18
申请号：US09521095
申请日：2000-03-07
申请人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
发明人： David L. Dickerson , Richard H. Lane , Charles H. Dennison , Kunal R. Parekh , Mark Fischer , John K. Zahurak
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/0332 , H01L21/76235
摘要： In one aspect, the invention includes an isolation region forming method comprising: a) forming an oxide layer over a substrate; b) forming a nitride layer over the oxide layer, the nitride layer and oxide layer having a pattern of openings extending therethrough to expose portions of the underlying substrate; c) etching the exposed portions of the underlying substrate to form openings extending into the substrate; d) after etching the exposed portions of the underlying substrate, removing portions of the nitride layer while leaving some of the nitride layer remaining over the substrate; and e) after removing portions of the nitride layer, forming oxide within the openings in the substrate, the oxide within the openings forming at least portions of isolation regions. In another aspect, the invention includes an isolation region forming method comprising: a) forming a silicon nitride layer over a substrate; b) forming a masking layer over the silicon nitride layer; c) forming a pattern of openings extending through the masking layer to the silicon nitride layer; d) extending the openings through the silicon nitride layer to the underlying substrate, the silicon nitride layer having edge regions proximate the openings and having a central region between the edge regions; e) extending the openings into the underlying substrate; f) after extending the openings into the underlying substrate, reducing a thickness of the silicon nitride layer at the edge regions to thin the edge regions relative to the central region; and g) forming oxide within the openings.
摘要翻译：一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氧化物层; b）在所述氧化物层上形成氮化物层，所述氮化物层和氧化物层具有延伸穿过其中的开口图案以暴露所述下面的衬底的部分; c）蚀刻下面的衬底的暴露部分以形成延伸到衬底中的开口; d）在蚀刻下面的衬底的暴露部分之后，去除氮化物层的部分，同时留下一些保留在衬底上的氮化物层; 以及e）在去除所述氮化物层的部分之后，在所述衬底的所述开口内形成氧化物，所述开口内的氧化物形成至少部分隔离区域。另一方面，本发明包括一种隔离区形成方法，包括：a）在衬底上形成氮化硅层; b）在氮化硅层上形成掩模层; c）形成延伸穿过掩模层的开口图案到氮化硅层; d）将开口穿过氮化硅层延伸到下面的衬底，氮化硅层具有靠近开口的边缘区域，并且在边缘区域之间具有中心区域; e）将开口延伸到下面的基底中; f）在将开口延伸到下面的基底之后，减小边缘区域处的氮化硅层的厚度，以使边缘区域相对于中心区域变薄; 和g）在开口内形成氧化物。

35. 发明授权

US06281083B1 Methods of forming field effect transistor gates, and methods of forming integrated circuitry 有权
标题翻译：形成场效应晶体管栅极的方法，以及形成集成电路的方法
公开(公告)号：US06281083B1
公开(公告)日：2001-08-28
申请号：US09559987
申请日：2000-04-26
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21336
CPC分类号： H01L23/485 , H01L21/76877 , H01L29/4933 , H01L2924/0002 , H01L2924/00
摘要： A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises semiconductive material conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion of first or second type conductivity enhancing impurity received thereover. An insulative layer is formed over the gate. An opening is formed into the insulative layer to a conductive portion of the gate. Semiconductive material conductively doped with a conductivity enhancing impurity of a second type is formed within the opening in electrical connection with the conductive portion, with the conductive diffusion barrier layer of the gate being received between the semiconductive material of the gate and the semiconductive material within the opening. Other aspects are disclosed and claimed.
摘要翻译：形成集成电路的方法包括在衬底上形成场效应晶体管栅极。栅极包括导电掺杂第一类型的导电性增强杂质的半导体材料和导电扩散阻挡层，以扩散其上接收的第一或第二类型导电性增强杂质。在栅极上形成绝缘层。开口形成在绝缘层中的栅极的导电部分上。导电地掺杂有第二类型的导电性增强杂质的半导体材料形成在与导电部分电连接的开口内，栅极的导电扩散阻挡层被接纳在栅极的半导电材料和内部的半导电材料之间开放公开和要求保护的其它方面。

36. 发明授权

US06251714B1 Method of making thin film field effect transistors 失效
标题翻译：制造薄膜场效应晶体管的方法
公开(公告)号：US06251714B1
公开(公告)日：2001-06-26
申请号：US08989366
申请日：1997-12-12
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2184
CPC分类号： H01L29/66757 , H01L27/11 , H01L27/1108 , H01L29/6675 , H01L29/66765 , H01L29/78618 , H01L29/78678
摘要： A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
摘要翻译：薄膜场效应晶体管包括：a）薄膜沟道区; b）与薄膜通道区相邻的一对相对的导电的第一和第二源/漏区; c）栅极绝缘体和位于薄膜通道区域附近的栅极，用于对沟道区域进行电激励以导通薄膜场效应晶体管; d）具有第一厚度的第一源极/漏极区域，第二源极/漏极区域具有第二厚度，沟道区域具有第三厚度; 第一和第二厚度中的至少一个大于第三厚度。公开了制造薄场效应晶体管的方法。

37. 发明授权

US06229212B1 Integrated circuitry and thin film transistors 有权
标题翻译：集成电路和薄膜晶体管
公开(公告)号：US06229212B1
公开(公告)日：2001-05-08
申请号：US09416818
申请日：1999-10-12
申请人： Charles H. Dennison , Monte Manning
发明人： Charles H. Dennison , Monte Manning
IPC分类号： H01L2348
CPC分类号： H01L29/6675 , H01L27/11 , H01L27/1108 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78648 , H01L2924/0002 , Y10S257/903 , H01L2924/00
摘要： An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
摘要翻译：电互连方法包括：a）在半导体晶片上提供由绝缘材料隔开的两个导电层; b）蚀刻导电层和绝缘材料以限定和向外暴露每个导电层的侧壁; c）在蚀刻的导电层及其各自的侧壁上沉积导电材料; 以及d）各向异性蚀刻所述导电材料以限定将所述两个导电层电连接的导电侧壁连接件。这样可用于制造薄膜晶体管和其他电路。

38. 再颁专利

USRE37104E1 Planarization of a gate electrode for improved gate patterning over non-planar active area isolation 失效
标题翻译：用于在非平面有源区隔离上改善栅极图案化的栅电极的平面化
公开(公告)号：USRE37104E1
公开(公告)日：2001-03-20
申请号：US08710287
申请日：1996-09-12
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21306
CPC分类号： H01L21/28123 , H01L21/7684
摘要： The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology topography of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.
摘要翻译：本发明是一种在非平面起始衬底上提供平面化晶体管栅极的方法，通过沉积覆盖相邻场氧化物隔离区域的平坦化导电多晶硅材料层，使得导电多晶硅材料的高度延伸到拓扑场地氧化物隔离区的形貌; 将导电硅化物材料层沉积在导电多晶硅材料上方并共同延伸; 然后对平坦化的导电多晶硅材料和导电硅化物材料进行构图，从而形成平坦化的晶体管栅极。

39. 发明授权

US06084289A Semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass, and a semiconductor structure 失效
标题翻译：在与场隔离物质相邻的区域形成接触开口的半导体加工方法以及半导体结构
公开(公告)号：US06084289A
公开(公告)日：2000-07-04
申请号：US95773
申请日：1998-06-10
申请人： Trung Tri Doan , Charles H. Dennison
发明人： Trung Tri Doan , Charles H. Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/76 , H01L21/762 , H01L21/768 , H01L23/485 , H01L29/78 , H01L23/58 , H01L29/76 , H01L29/94
CPC分类号： H01L21/76897 , H01L21/76224 , H01L21/76802 , H01L23/485 , H01L2924/0002 , Y10S148/05
摘要： A semiconductor processing method of forming a contact opening to a region adjacent a field isolation mass includes, a) forming a field isolation mass within a semiconductor substrate by a trench and refill technique, and a substrate masking layer over the substrate adjacent the field isolation mass, the field isolation mass being capped with an etch stop cap, the field isolation mass having a sidewall covered by the masking layer; b) removing the substrate masking layer away from the isolation mass to expose at least a portion of the isolation mass sidewall; c) forming an etch stop cover over the exposed isolation mass sidewall; d) forming an insulating layer over the isolation mass and substrate area adjacent the isolation mass; and e) etching a contact opening through the insulating layer to adjacent the isolation mass selectively relative to the isolation mass etch stop cap and cover. A semiconductor structure is also described.
摘要翻译：在与场隔离物质相邻的区域形成接触开口的半导体处理方法包括：a）通过沟槽和再填充技术在半导体衬底内形成场隔离块，以及在与衬底相邻的场隔离质量所述场隔离物质被蚀刻停止盖封盖，所述场隔离块具有由所述掩蔽层覆盖的侧壁; b）将所述衬底掩模层从所述隔离块上移除以暴露所述隔离质量侧壁的至少一部分; c）在暴露的隔离质量侧壁上形成蚀刻停止盖; d）在邻近隔离块的隔离物质和衬底区域上形成绝缘层; 以及e）相对于所述隔离质量蚀刻停止帽和覆盖物，选择性地蚀刻通过所述绝缘层的接触开口以邻近所述隔离物质。还描述了半导体结构。

40. 发明授权

US6074902A Method of forming complementary type conductive regions on a substrate 失效
标题翻译：在基板上形成互补型导电区域的方法
公开(公告)号：US6074902A
公开(公告)日：2000-06-13
申请号：US996086
申请日：1997-12-22
申请人： Trung Tri Doan , Charles H. Dennison
发明人： Trung Tri Doan , Charles H. Dennison
IPC分类号： H01L21/8238
CPC分类号： H01L21/82385 , H01L21/823842
摘要： A method of forming complementary type conductive regions on a substrate includes, a) providing a first etch stop layer over a substrate; b) etching a void through the first etch stop layer inwardly towards the substrate; c) providing a first conductive layer of a first conductive material over the first etch stop layer and into the void; d) removing the first conductive layer over the first etch stop layer to eliminate all first conductive material from atop the first etch stop layer, and leaving first conductive material in the void; e) removing the remaining first etch stop layer from the substrate thereby defining a remaining region of first conductive layer; f) providing a second conductive layer of a second conductive material over the substrate and remaining first conductive layer region; and g) removing the second conductive layer over the first conductive layer to eliminate all second is conductive material from atop the first conductive layer, and leaving second conductive material atop the substrate which is adjacent the projecting first conductive material region.
摘要翻译：在衬底上形成互补型导电区域的方法包括：a）在衬底上提供第一蚀刻停止层; b）通过第一蚀刻停止层向衬底内部蚀刻空隙; c）在所述第一蚀刻停止层上并在所述空隙中提供第一导电材料的第一导电层; d）去除第一蚀刻停止层上的第一导电层以从第一蚀刻停止层顶部消除所有第一导电材料，并将第一导电材料留在空隙中; e）从衬底去除剩余的第一蚀刻停止层，从而限定第一导电层的剩余区域; f）在所述衬底上提供第二导电材料的第二导电层和剩余的第一导电层区域; 以及g）在所述第一导电层上移除所述第二导电层以从所述第一导电层顶部消除所有第二导电材料，并且在所述基板的顶部与所述突出的第一导电材料区域相邻地留下第二导电材料。

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