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31. 发明申请

US20070238233A1 Method of making a multiple crystal orientation semiconductor device 有权
标题翻译：制造多晶体取向半导体器件的方法
公开(公告)号：US20070238233A1
公开(公告)日：2007-10-11
申请号：US11393563
申请日：2006-03-30
申请人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
发明人： Mariam Sadaka , Bich-Yen Nguyen , Ted White
IPC分类号： H01L21/337
CPC分类号： H01L21/84 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.
摘要翻译：以增强的性能晶体取向形成的晶体管的方法从具有第一表面取向的半导体衬底（12,52），半导体衬底上的薄蚀刻停止层（14,54），掩埋氧化物层（ 16,56）和在所述掩埋氧化物层上的第二表面取向的半导体层（18,58）。蚀刻渗透到薄的蚀刻停止层。被选择以最小化对下面的半导体衬底的损害的另一蚀刻暴露了半导体衬底的一部分。然后从半导体衬底的暴露部分生长外延半导体（28,66）以形成具有第一表面取向并且具有很少（如果有的话）缺陷的半导体区域。然后外延生长的半导体区域用于增强一种类型的晶体管，而第二表面取向的半导体层用于增强不同类型的晶体管。

32. 发明申请

US20070215908A1 Electronic device including a semiconductor fin and a process for forming the electronic device 有权
标题翻译：包括半导体鳍片的电子设备和用于形成电子设备的工艺
公开(公告)号：US20070215908A1
公开(公告)日：2007-09-20
申请号：US11375894
申请日：2006-03-15
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66507 , H01L29/66795 , H01L29/78684
摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.
摘要翻译：电子器件可以包括覆盖绝缘层的半导体鳍片。电子器件还可以包括覆盖半导体鳍片的半导体层。半导体层可以具有彼此间隔开的第一部分和第二部分。在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。电子器件还可以包括覆盖半导体层的金属 - 半导体层。在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

33. 发明申请

US20070184601A1 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20070184601A1
公开(公告)日：2007-08-09
申请号：US11349595
申请日：2006-02-08
申请人： Da Zhang , Bich-Yen Nguyen
发明人： Da Zhang , Bich-Yen Nguyen
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate having a first doped region and a second doped region, providing a dielectric over the first doped region and the second doped region, and forming a first gate stack over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion over the dielectric, a first in situ doped semiconductor portion over the metal portion, and a first blocking cap over the in situ doped semiconductor portion. The method further includes performing implantations to form source/drain regions adjacent the first and second gate stack, where the first blocking cap has a thickness sufficient to substantially block implant dopants from entering the first in situ doped semiconductor portion. Source/drain embedded stressors are also formed.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底，在第一掺杂区域和第二掺杂区域上提供电介质，以及在电介质上至少形成第一栅极叠层第一掺杂区域的一部分。第一栅极堆叠包括电介质上的金属部分，金属部分上方的第一原位掺杂半导体部分以及原位掺杂半导体部分上的第一阻挡盖。该方法还包括执行注入以形成与第一和第二栅极堆叠相邻的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡注入掺杂剂进入第一原位掺杂半导体部分的厚度。源/漏嵌入式应力源也形成。

34. 发明申请

US20070171700A1 Electronic device including a static-random-access memory cell and a process of forming the electronic device 有权
标题翻译：包括静态随机存取存储单元的电子设备和形成电子设备的过程
公开(公告)号：US20070171700A1
公开(公告)日：2007-07-26
申请号：US11337355
申请日：2006-01-23
申请人： James Burnett , Bich-Yen Nguyen , Brian Winstead
发明人： James Burnett , Bich-Yen Nguyen , Brian Winstead
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/845 , H01L27/1211 , H01L29/045
摘要： An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.
摘要翻译：电子设备可以包括静态随机存取存储器单元。静态随机存取存储器单元可以包括第一类型的第一晶体管和第二类型的第二晶体管。第一晶体管可以具有沿着第一线延伸的第一沟道长度，并且第二晶体管可以具有沿着第二线延伸的第二沟道长度。第一行和第二行可以以不同于22.5°的整数倍的值相交。在特定实施例中，第一晶体管可以包括上拉晶体管，并且第二晶体管可以包括通过栅极或下拉晶体管。可以使用一种方法来形成包括栅电极部分的半导体鳍片和导电构件，以实现包括第一和第二晶体管的电子器件。

35. 发明授权

US07241647B2 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US07241647B2
公开(公告)日：2007-07-10
申请号：US10919952
申请日：2004-08-17
申请人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam G. Sadaka , Shawn G. Thomas , Ted R. White , Chun-Li Liu , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/00
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

36. 发明授权

US07208357B2 Template layer formation 有权
标题翻译：模板层形成
公开(公告)号：US07208357B2
公开(公告)日：2007-04-24
申请号：US10919922
申请日：2004-08-17
申请人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
发明人： Mariam G. Sadaka , Alexander L. Barr , Bich-Yen Nguyen , Voon-Yew Thean , Ted R. White
IPC分类号： H01L21/00 , H01L21/20 , H01L21/425
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e.g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在层之前进行冷凝过程之前将离子注入到半导体层中。离子有助于半导体层中的原子（例如锗）的扩散并增加半导体层的松弛。在冷凝过程之后，该层可用作形成应变半导体层的模板层。

37. 发明授权

US07141857B2 Semiconductor structures and methods of fabricating semiconductor structures comprising hafnium oxide modified with lanthanum, a lanthanide-series metal, or a combination thereof 有权
公开(公告)号：US07141857B2
公开(公告)日：2006-11-28
申请号：US10883180
申请日：2004-06-30
申请人： Zhiyi Yu , Jay A. Curless , Yong Liang , Alexandra Navrotsky , Sergey Ushakov , Bich-Yen Nguyen , Alexander Demkov
发明人： Zhiyi Yu , Jay A. Curless , Yong Liang , Alexandra Navrotsky , Sergey Ushakov , Bich-Yen Nguyen , Alexander Demkov
IPC分类号： H01L29/94 , H01L21/469
CPC分类号： H01L21/02181 , C23C14/0026 , C23C14/083 , H01L21/02192 , H01L21/0234 , H01L21/28194 , H01L21/3115 , H01L21/31645 , H01L29/513 , H01L29/517
摘要： Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.

38. 发明申请

US20060228872A1 Method of making a semiconductor device having an arched structure strained semiconductor layer 审中-公开
标题翻译：制造具有拱形结构应变半导体层的半导体器件的方法
公开(公告)号：US20060228872A1
公开(公告)日：2006-10-12
申请号：US11093645
申请日：2005-03-30
申请人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
发明人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
IPC分类号： H01L21/20
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A method of forming a semiconductor device includes forming a local strain-inducing structure of a first semiconductor material at a point location within a dielectric layer. The local strain-inducing structure has a prescribed geometry with a surface disposed above a surface of the dielectric layer. A second semiconductor material is formed over the dielectric layer and the local strain inducing structure, wherein formation of a first portion of the second material over the dielectric layer provides a poly crystalline structure of the second material and wherein formation of a second portion of the second material over the local strain-inducing structure provides a single crystalline structure of the second material subject to mechanical strain by the surface of the local strain-inducing structure. The single crystalline structure serves as a strained semiconductor layer of the semiconductor device.
摘要翻译：形成半导体器件的方法包括在电介质层内的点位置形成第一半导体材料的局部应变诱导结构。局部应变诱导结构具有规定的几何形状，其表面设置在电介质层的表面之上。第二半导体材料形成在电介质层和局部应变诱导结构之上，其中第二材料的第一部分在电介质层上的形成提供了第二材料的多晶结构，并且其中形成第二材料的第二部分局部应变诱导结构上的材料提供由局部应变诱导结构的表面经受机械应变的第二材料的单晶结构。单晶结构用作半导体器件的应变半导体层。

39. 发明申请

US20060226492A1 Semiconductor device featuring an arched structure strained semiconductor layer 审中-公开
标题翻译：具有拱形结构的半导体器件应变半导体层
公开(公告)号：US20060226492A1
公开(公告)日：2006-10-12
申请号：US11094008
申请日：2005-03-30
申请人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
发明人： Bich-Yen Nguyen , Shawn Thomas , Lubomir Cergel , Mariam Sadaka , Voon-Yew Thean , Peter Wennekers , Ted White , Andreas Wild , Detlev Gruetzmacher , Oliver Schmidt
IPC分类号： H01L29/94
CPC分类号： H01L29/78696 , H01L29/0649 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.
摘要翻译：半导体器件包括机械应变通道，其中通道包括具有非线性几何形状的应变半导体层的单晶结构，非线性几何形状包括拱形部分。所述半导体器件还包括介电层，其中所述沟道的第一部分设置在所述电介质层内的点位置上方，并且所述沟道的第二部分设置在所述电介质层的靠近所述点位置和外部的位置。此外，栅极靠近通道设置，用于控制电流通过耦合到通道的第一和第二电流处理电极之间的通道。

40. 发明授权

US06518106B2 Semiconductor device and a method therefor 有权
公开(公告)号：US06518106B2
公开(公告)日：2003-02-11
申请号：US09865855
申请日：2001-05-26
申请人： Tat Ngai , Bich-Yen Nguyen , Vidya S. Kaushik , Jamie K. Schaeffer
发明人： Tat Ngai , Bich-Yen Nguyen , Vidya S. Kaushik , Jamie K. Schaeffer
IPC分类号： H01L2100
CPC分类号： H01L21/823842
摘要： A semiconductor device with dual gate electrodes and its method of formation is taught. A first metal/silicon gate stack and a first gate dielectric are formed over a first doped region. The metal/gate stack comprises a metal portion over the first gate dielectric and a first gate portion over the metal portion. A silicon gate and a second gate dielectric are formed over the second doped region. In one embodiment, the first and second gate portions are P+ doped silicon germanium and the metal portion is TaSiN. In another embodiment, the first and second gate portions are N+ doped polysilicon and the metal portion is TaSiN.

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