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1. 发明申请

US20070171700A1 Electronic device including a static-random-access memory cell and a process of forming the electronic device 有权
标题翻译：包括静态随机存取存储单元的电子设备和形成电子设备的过程
公开(公告)号：US20070171700A1
公开(公告)日：2007-07-26
申请号：US11337355
申请日：2006-01-23
申请人： James Burnett , Bich-Yen Nguyen , Brian Winstead
发明人： James Burnett , Bich-Yen Nguyen , Brian Winstead
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/845 , H01L27/1211 , H01L29/045
摘要： An electronic device can include a static-random-access memory cell. The static-random-access memory cell can include a first transistor of a first type and a second transistor of a second type. The first transistor can have a first channel length extending along a first line, and the second transistor can have a second channel length extending along a second line. The first line and the second line can intersect at an angle having a value other than any integer multiple of 22.5°. In a particular embodiment, the first transistor can include a pull-up transistor, and the second transistor can include a pass gate or pull-down transistor. A process can be used to form semiconductor fins and conductive members, which include gate electrode portions, to achieve the electronic device including the first and second transistors.
摘要翻译：电子设备可以包括静态随机存取存储器单元。静态随机存取存储器单元可以包括第一类型的第一晶体管和第二类型的第二晶体管。第一晶体管可以具有沿着第一线延伸的第一沟道长度，并且第二晶体管可以具有沿着第二线延伸的第二沟道长度。第一行和第二行可以以不同于22.5°的整数倍的值相交。在特定实施例中，第一晶体管可以包括上拉晶体管，并且第二晶体管可以包括通过栅极或下拉晶体管。可以使用一种方法来形成包括栅电极部分的半导体鳍片和导电构件，以实现包括第一和第二晶体管的电子器件。

2. 发明申请

US20070093043A1 Semiconductor structure with reduced gate doping and methods for forming thereof 有权
标题翻译：减少栅极掺杂的半导体结构及其形成方法
公开(公告)号：US20070093043A1
公开(公告)日：2007-04-26
申请号：US11260849
申请日：2005-10-26
申请人： Brian Winstead , James Burnett , Sinan Goktepeli
发明人： Brian Winstead , James Burnett , Sinan Goktepeli
IPC分类号： H01L21/04
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.
摘要翻译：半导体结构包括具有存储区域和逻辑区域的衬底。第一p型器件形成在存储器区域中，并且第二p型器件形成在逻辑区域中。第一p型器件的半导体栅极的至少一部分具有比第二p型器件的半导体栅极的至少一部分更低的p型掺杂剂浓度。第一和第二p型器件的半导体栅极各自具有非零p型掺杂剂浓度。

3. 发明申请

US20070158764A1 Electronic device including a fin-type transistor structure and a process for forming the electronic device 有权
标题翻译：包括鳍型晶体管结构的电子器件和用于形成电子器件的工艺
公开(公告)号：US20070158764A1
公开(公告)日：2007-07-12
申请号：US11328594
申请日：2006-01-10
申请人： Marius Orlowski , James Burnett
发明人： Marius Orlowski , James Burnett
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/66795
摘要： An electronic device can include an insulating layer and a fin-type transistor structure. The fin-type structure can have a semiconductor fin and a gate electrode spaced apart from each other. A dielectric layer and a spacer structure can lie between the semiconductor fin and the gate electrode. The semiconductor fin can include channel region including a portion associated with a relatively higher VT lying between a portion associated with a relatively lower VT and the insulating layer. In one embodiment, the supply voltage is lower than the relatively higher VT of the channel region. A process for forming the electronic device is also disclosed.
摘要翻译：电子器件可以包括绝缘层和鳍型晶体管结构。翅片型结构可以具有彼此间隔开的半导体翅片和栅电极。电介质层和间隔结构可以位于半导体鳍片和栅电极之间。半导体鳍片可以包括沟道区域，该沟道区域包括与相对较低V T T T相关的部分与绝缘层之间相对较高的V SUB相关联的部分。在一个实施例中，电源电压低于沟道区的相对较高的V SUB。还公开了一种用于形成电子器件的工艺。

4. 发明申请

US20070112049A1 Small Molecule Inhibitors of Botulinum Neurotoxins 失效
标题翻译：肉毒杆菌神经毒素的小分子抑制剂
公开(公告)号：US20070112049A1
公开(公告)日：2007-05-17
申请号：US11464007
申请日：2006-08-11
申请人： Sina Bavari , Rick Gussio , James Burnett
发明人： Sina Bavari , Rick Gussio , James Burnett
IPC分类号： A61K31/427 , A61K31/423 , A61K31/4184
CPC分类号： A61K31/4184 , A61K31/423 , A61K31/427 , A61K31/428 , C07D209/10 , C07D209/12 , C07D209/14 , C07D333/56 , C07D333/60 , C07D401/06 , C07D401/12 , C07D403/04 , C07D405/06 , C07D405/14 , C07D407/06 , C07D409/04 , Y02A50/406 , Y02A50/473
摘要： Disclosed herein are methods of inhibiting the activity of Botulinum neurotoxin A metalloprotease with the compounds disclosed herein. Also disclosed are methods of treating, inhibiting or preventing intoxication caused by bacteria of at least one bacterial strain in a subject, and pharmaceutical and cosmetic compositions comprising the compounds disclosed herein.
摘要翻译：本文公开的是使用本文公开的化合物抑制肉毒杆菌神经毒素A金属蛋白酶的活性的方法。还公开了治疗，抑制或预防受试者中至少一种细菌菌株的细菌引起的中毒的方法，以及包含本文公开的化合物的药物和化妆品组合物。

5. 发明申请

US20050156229A1 Integrated circuit device and method therefor 审中-公开
公开(公告)号：US20050156229A1
公开(公告)日：2005-07-21
申请号：US11014661
申请日：2004-12-16
申请人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
发明人： Geoffrey Yeap , Srinivas Jallepalli , Yongjoo Jeon , James Burnett , Rana Singh , Paul Grudowski
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L29/76 , H01L29/78
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/1052 , H01L27/11541 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

6. 发明申请

US20050153945A1 Small molecules and a pharmacophore model for inhibition of botulinum toxin and methods of making and using thereof 失效
标题翻译：用于抑制肉毒杆菌毒素的小分子和药效团模型及其制备和使用方法
公开(公告)号：US20050153945A1
公开(公告)日：2005-07-14
申请号：US10935622
申请日：2004-09-08
申请人： Sina Bavari , James Schmidt , James Burnett , Rick Gussio
发明人： Sina Bavari , James Schmidt , James Burnett , Rick Gussio
IPC分类号： A61K31/4709 , A61K31/473 , A61K31/555 , A61K31/63 , C07K20060101 , G01N33/48 , G01N33/50 , G01N33/53 , G06F19/00
CPC分类号： A61K31/635 , A61K31/47 , A61K31/4706 , A61K45/06 , G06F19/705 , G06F19/706 , A61K2300/00
摘要： Disclosed herein is a pharmacophore model for inhibiting Botulinum neurotoxin A metalloprotease activity which comprises a first plane A, a second plane B, a first hydrophobic moiety C, a second hydrophobic moiety D and a positive ionizable substituent E. The pharmacophore model may further comprise a heteroatom in the first plane A. In some embodiments, the distance between the center of the first plane A and the center of the second plane B is about 6.5 to about 9.5 Å. In some embodiments, the distance between the center of the first hydrophobic moiety C and the center of the second hydrophobic moiety D is about 8.0 to about 16.0 Å. In some embodiments, the distance between the center of the first plane to the center of the first hydrophobic moiety C is about 3.0 to about 5.0 Å. In some embodiments, the distance between the center of the second plane to the center of the second hydrophobic moiety C is about 3.0 to about 5.0 Å. In some embodiments, the distance between the center of the first plane to the center of the positive ionizable substituent is about 6.5 to about 9.5 Å.
摘要翻译：本文公开了用于抑制肉毒杆菌神经毒素A金属蛋白酶活性的药效团模型，其包含第一平面A，第二平面B，第一疏水部分C，第二疏水部分D和可阳离子化取代基E.药效基团模型还可包含在一些实施例中，第一平面A的中心与第二平面B的中心之间的距离为约6.5至约9.5。在一些实施方案中，第一疏水部分C的中心与第二疏水部分D的中心之间的距离为约8.0至约16.0。在一些实施方案中，第一平面的中心与第一疏水部分C的中心之间的距离为约3.0至约5.0。在一些实施方案中，第二平面的中心与第二疏水部分C的中心之间的距离为约3.0至约5.0。在一些实施方案中，第一平面的中心与正电离取代基的中心之间的距离为约6.5至约9.5。

7. 发明申请

US20070211526A1 Switch device and method 有权
标题翻译：开关装置及方法
公开(公告)号：US20070211526A1
公开(公告)日：2007-09-13
申请号：US11373532
申请日：2006-03-10
申请人： James Burnett
发明人： James Burnett
IPC分类号： G11C11/34 , G11C11/00
CPC分类号： G11C11/413 , G11C7/02 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A device is disclosed having a first Field Effect Transistor having a channel region controlled by a gate, a second Field Effect Transistor having a first channel region substantially controlled by a first gate, and a second channel region substantially controlled by a second gate. The gate of the first Field Effect Transistor and the first gate of the second Field Effect Transistor are coupled to a memory write line. The second gate of the second Field Effect Transistor receives a control signal from a memory bit cell.
摘要翻译：公开了一种具有第一场效应晶体管的器件，其具有由栅极控制的沟道区域，第二场效应晶体管具有基本由第一栅极控制的第一沟道区域和由第二栅极基本控制的第二沟道区域。第一场效应晶体管的栅极和第二场效应晶体管的第一栅极耦合到存储器写入线。第二场效应晶体管的第二栅极从存储器位单元接收控制信号。

8. 发明申请

US20070093054A1 Multiple device types including an inverted-T channel transistor and method therefor 有权
标题翻译：多种器件类型，包括反向T沟道晶体管及其方法
公开(公告)号：US20070093054A1
公开(公告)日：2007-04-26
申请号：US11257972
申请日：2005-10-25
申请人： Byoung Min , James Burnett , Leo Mathew
发明人： Byoung Min , James Burnett , Leo Mathew
IPC分类号： H01L21/4763 , H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成具有在垂直有源区两侧延伸的垂直有源区和水平有源区的第一晶体管。该方法还包括形成具有垂直有源区的第二晶体管。该方法还包括形成具有垂直有源区和仅在垂直有源区的一侧上延伸的水平有源区的第三晶体管。

9. 发明申请

US20070089662A1 STAINLESS STEEL-PLATED BOAT HULL SYSTEM AND METHOD 审中-公开
标题翻译：不锈钢船体系统及方法
公开(公告)号：US20070089662A1
公开(公告)日：2007-04-26
申请号：US11538288
申请日：2006-10-03
申请人： James Burnett
发明人： James Burnett
IPC分类号： B63B3/00
CPC分类号： B63B3/16 , B63B9/04
摘要： A stainless-steel boat hull system and method. Exemplary embodiments include a method of maintaining steel-hulled boats, including accessing a steel boat hull, removing surface layers of the boat hull, identifying structurally supportive layers of the boat hull, priming the boat hull, attaching pre-selected stainless steel plates to the boat hull in an overlapped arrangement and connecting adjacent stainless steel plates.
摘要翻译：不锈钢船体系统及方法。示例性实施例包括维持钢船的方法，包括进入钢船体，移除船体的表面层，识别船体的结构上支撑层，起动船体，将预先选定的不锈钢板连接到船体重叠布置并连接相邻的不锈钢板。

10. 发明申请

US20070057329A1 Semiconductor device having a p-MOS transistor with source-drain extension counter-doping 审中-公开
标题翻译：具有源极 - 漏极延伸反掺杂的p-MOS晶体管的半导体器件
公开(公告)号：US20070057329A1
公开(公告)日：2007-03-15
申请号：US11222544
申请日：2005-09-09
申请人： Sinan Goktepeli , James Burnett
发明人： Sinan Goktepeli , James Burnett
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L21/823814
摘要： A method for forming a semiconductor device is provided. The method includes forming a n-type well region. The method further includes forming a gate corresponding to the semiconductor device on top of the n-type well region. The method further includes forming a source-drain extension region on each side of the gate in the n-type well region using a p-type dopant. The method further includes doping the source-drain extension region on each side of the gate in the n-type well region using a n-type dopant such that the n-type dopant is substantially encompassed within the source-drain extension region. The method further includes forming a source and a drain corresponding to the semiconductor device.
摘要翻译：提供一种形成半导体器件的方法。该方法包括形成n型阱区域。该方法还包括在n型阱区域的顶部上形成与半导体器件对应的栅极。该方法还包括使用p型掺杂剂在n型阱区域中的栅极的每一侧上形成源极 - 漏极延伸区域。该方法还包括使用n型掺杂剂在n型阱区域中的栅极的每侧上掺杂源极 - 漏极延伸区域，使得n型掺杂剂基本上包围在源极 - 漏极延伸区域内。该方法还包括形成对应于半导体器件的源极和漏极。

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