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31. 发明授权

US09076510B2 Power mixing circuit and semiconductor memory device including the same 有权
标题翻译：功率混合电路和包括其的半导体存储器件
公开(公告)号：US09076510B2
公开(公告)日：2015-07-07
申请号：US13619793
申请日：2012-09-14
申请人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
发明人： Young-Chul Cho , Young-Jin Jeon , Yong-Cheol Bae
IPC分类号： G11C5/14 , G11C7/02 , G11C7/10 , G11C7/20 , G11C5/04
CPC分类号： G11C5/147 , G11C5/04 , G11C5/148 , G11C7/02 , G11C7/1012 , G11C7/1057 , G11C7/20
摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power-down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.
摘要翻译：提供了能够在深度掉电模式下保持稳定的输出电压的功率混合电路。功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。

32. 发明授权

US08984475B2 Apparatus and method for generating code overlay 有权
标题翻译：用于生成代码叠加的装置和方法
公开(公告)号：US08984475B2
公开(公告)日：2015-03-17
申请号：US13045576
申请日：2011-03-11
申请人： Soo-Jung Ryu , Choon-Ki Jang , Jaejin Lee , Bernhard Egger , Young-Chul Cho
发明人： Soo-Jung Ryu , Choon-Ki Jang , Jaejin Lee , Bernhard Egger , Young-Chul Cho
IPC分类号： G06F9/44 , G06F9/45 , G06F12/02
CPC分类号： G06F12/0223
摘要： Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.
摘要翻译：提供了一种用于生成能够最小化存储器拷贝数量的代码覆盖的装置和方法。生成静态时间关系图（STRG），其中程序的每个功能对应于STRG的节点，而冲突的未命中值对应于STRG的边。冲突错值是功能之间可能的冲突错过的最大数量。通过从STRG中选择至少一个功能来产生覆盖，当分配至少一个所选择的功能时，计算要给予的存储器的每个区域的分配成本，并且将至少一个所选择的功能分配给具有分配成本最小

33. 发明授权

US08930672B2 Multiprocessor using a shared virtual memory and method of generating a translation table 有权
标题翻译：使用共享虚拟内存的多处理器和生成转换表的方法
公开(公告)号：US08930672B2
公开(公告)日：2015-01-06
申请号：US13074999
申请日：2011-03-29
申请人： Choon-Ki Jang , Jaejin Lee , Soo-Jung Ryu , Bernhard Egger , Yoon-Jin Kim , Woong Seo , Young-Chul Cho
发明人： Choon-Ki Jang , Jaejin Lee , Soo-Jung Ryu , Bernhard Egger , Yoon-Jin Kim , Woong Seo , Young-Chul Cho
IPC分类号： G06F13/00 , G06F13/28 , G06F12/10
CPC分类号： G06F12/1072 , Y02D10/13
摘要： A multiprocessor using a shared virtual memory (SVM) is provided. The multiprocessor includes a plurality of processing cores and a memory manager configured to transform a virtual address into a physical address to allow a processing core to access a memory region corresponding to the physical address.
摘要翻译：提供了使用共享虚拟内存（SVM）的多处理器。所述多处理器包括多个处理核心和存储器管理器，所述存储器管理器被配置为将虚拟地址变换为物理地址，以允许处理核心访问对应于所述物理地址的存储器区域。

34. 发明申请

US20130182513A1 MEMORY SYSTEM CAPABLE OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CALIBRATING OUTPUT VOLTAGE LEVEL OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于校准半导体存储器件的输出电压水平的存储器系统和校准半导体存储器件的输出电压水平的方法
公开(公告)号：US20130182513A1
公开(公告)日：2013-07-18
申请号：US13611867
申请日：2012-09-12
申请人： Yoon-Joo EOM , Young-Jin JEON , Yong-Cheol BAE , Young-Chul CHO
发明人： Yoon-Joo EOM , Young-Jin JEON , Yong-Cheol BAE , Young-Chul CHO
IPC分类号： G11C5/14 , H03K19/003 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/021 , G11C29/028 , G11C2207/2254 , H03K19/0005
摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.
摘要翻译：提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。存储器系统包括存储器控制器和半导体存储器件。半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。

35. 发明申请

US20120221797A1 MULTI-PORT CACHE MEMORY APPARATUS AND METHOD 有权
标题翻译：多端口高速缓存存储器和方法
公开(公告)号：US20120221797A1
公开(公告)日：2012-08-30
申请号：US13362460
申请日：2012-01-31
申请人： Moo-Kyoung Chung , Soo-Jung Ryu , Ho-Young Kim , Woong Seo , Young-Chul Cho
发明人： Moo-Kyoung Chung , Soo-Jung Ryu , Ho-Young Kim , Woong Seo , Young-Chul Cho
IPC分类号： G06F12/08
CPC分类号： G06F12/0853 , G06F12/0846
摘要： Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.
摘要翻译：提供了一种多端口高速缓存存储装置和多端口高速缓存存储装置的方法。多端口存储装置可以将地址空间划分为地址区域，并将划分的存储区域分配给高速缓存存储体，从而防止对特定高速缓存的访问集中。

36. 发明申请

US20110238945A1 APPARATUS AND METHOD FOR GENERATING CODE OVERLAY 有权
标题翻译：用于产生代码重叠的装置和方法
公开(公告)号：US20110238945A1
公开(公告)日：2011-09-29
申请号：US13045576
申请日：2011-03-11
申请人： Soo-Jung Ryu , Choon-ki Jang , Jaejin Lee , Bernhard Egger , Young-Chul Cho
发明人： Soo-Jung Ryu , Choon-ki Jang , Jaejin Lee , Bernhard Egger , Young-Chul Cho
IPC分类号： G06F12/02
CPC分类号： G06F12/0223
摘要： Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost.
摘要翻译：提供了一种用于生成能够最小化存储器拷贝数量的代码覆盖的装置和方法。生成静态时间关系图（STRG），其中程序的每个功能对应于STRG的节点，而冲突的未命中值对应于STRG的边。冲突错值是功能之间可能的冲突错过的最大数量。通过从STRG中选择至少一个功能来产生覆盖，当分配至少一个所选择的功能时，计算要给予的存储器的每个区域的分配成本，并且将至少一个所选择的功能分配给具有分配成本最小

37. 发明授权

US07319631B2 Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same 有权
标题翻译：具有堆叠库结构的半导体存储器件和用于驱动其字线的方法
公开(公告)号：US07319631B2
公开(公告)日：2008-01-15
申请号：US11233700
申请日：2005-09-23
申请人： Young-Chul Cho
发明人： Young-Chul Cho
IPC分类号： G11C8/00
CPC分类号： G11C5/02 , G11C8/08 , G11C8/12 , G11C8/14
摘要： A semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks is disclosed. The semiconductor memory device includes memory bank groups and a decoder unit. Each of the memory bank groups includes a plurality of memory banks arranged in a stacked-bank architecture. The decoder unit generates a decoded row address signal to individually select one of the memory banks in response to an external address signal under the control of an output enable signal. Accordingly, the semiconductor memory device having a stacked-bank architecture capable of activating the word lines coupled to memory cells selectively with respect to the memory banks has lower power consumption and operates stably against noise.
摘要翻译：公开了一种半导体存储器件，其具有能够相对于存储体选择性地激活耦合到存储器单元的字线的堆叠库结构。半导体存储器件包括存储体组和解码器单元。存储体组中的每一个都包括以堆叠体架构布置的多个存储体。解码器单元产生解码行地址信号，以在输出使能信号的控制下响应于外部地址信号分别选择存储体之一。因此，具有能够相对于存储体选择性地激活耦合到存储器单元的字线的堆叠库结构的半导体存储器件具有较低的功耗并且能够稳定地抵抗噪声。

38. 发明授权

US07280383B2 Semiconductor memory device and a method for arranging signal lines thereof 有权
标题翻译：半导体存储器件及其信号线的布置方法
公开(公告)号：US07280383B2
公开(公告)日：2007-10-09
申请号：US11262530
申请日：2005-10-28
申请人： Young-Chul Cho , Sung-Hoon Kim , Joung-Yeal Kim
发明人： Young-Chul Cho , Sung-Hoon Kim , Joung-Yeal Kim
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： The present invention discloses a semiconductor memory device and a method for arranging signal lines thereof. The semiconductor memory device including a first memory cell array, an IO control circuit and a second memory cell array arranged between the first memory cell array and the IO control circuit, includes: first IO signal lines for transmitting data between the first memory cell array and the IO control circuit, wherein the first IO signal lines are connected to first data loading locations of the first memory cell array and extend in a straight line to the IO control circuit; and second IO signal lines for transmitting data between the second memory cell array and the IO control circuit, wherein the second IO signal lines are connected to first data loading locations of the second memory cell array and extend to the IO control circuit, wherein lengths of the first IO signal lines starting from the first data loading locations of the first memory cell array to the IO control circuit are identical to lengths of the second IO signal lines starting from the first data loading locations of the second memory cell array to the IO control circuit.
摘要翻译：本发明公开了一种半导体存储器件及其信号线的布置方法。包括第一存储单元阵列，IO控制电路和布置在第一存储单元阵列和IO控制电路之间的第二存储单元阵列的半导体存储器件包括：第一IO信号线，用于在第一存储单元阵列与第 IO控制电路，其中第一IO信号线连接到第一存储单元阵列的第一数据加载位置并且以直线延伸到IO控制电路; 以及第二IO信号线，用于在第二存储单元阵列和IO控制电路之间传输数据，其中第二IO信号线连接到第二存储单元阵列的第一数据加载位置并延伸到IO控制电路，其中，从第一存储单元阵列的第一数据加载位置开始到IO控制电路的第一IO信号线与从第二存储单元阵列的第一数据加载位置到IO控制开始的第二IO信号线的长度相同电路。

39. 发明申请

US20150339255A1 INPUT/OUTPUT INTERFACE 审中-公开
标题翻译：输入/输出接口
公开(公告)号：US20150339255A1
公开(公告)日：2015-11-26
申请号：US14818586
申请日：2015-08-05
申请人： Young Chul CHO , Jung Bae LEE , Jung Hwan CHOI
发明人： Young Chul CHO , Jung Bae LEE , Jung Hwan CHOI
IPC分类号： G06F13/42 , G05F1/625
CPC分类号： G06F13/16 , G05F1/625 , G06F1/3287 , G06F13/4068 , G06F13/4221 , H03K19/0005 , Y02D10/14 , Y02D10/151
摘要： A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
摘要翻译：操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

40. 发明申请

US20140152340A1 OPERATING METHOD OF INPUT/OUTPUT INTERFACE 有权
标题翻译：输入/输出接口的操作方法
公开(公告)号：US20140152340A1
公开(公告)日：2014-06-05
申请号：US14093916
申请日：2013-12-02
申请人： Young Chul CHO , Jung Bae LEE , Jung Hwan CHOI
发明人： Young Chul CHO , Jung Bae LEE , Jung Hwan CHOI
IPC分类号： H03K19/00
CPC分类号： G06F13/16 , G05F1/625 , G06F1/3287 , G06F13/4068 , G06F13/4221 , H03K19/0005 , Y02D10/14 , Y02D10/151
摘要： A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
摘要翻译：操作输入/输出接口的方法包括根据模式选择信号选择多个输出驱动器电路中的一个，并且使用多个输出驱动器电路中选择的一个输出驱动器电路来输出数据信号。另一种操作方法包括根据所接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的片上终端（ODT）电路。另一种操作方法包括基于接收的命令信号产生模式选择信号，并根据模式选择信号控制输入/输出接口中包括的ODT电路。

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