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    • 31. 发明授权
    • Etching method and structure using a hard mask for strained silicon MOS transistors
    • 用于应变硅MOS晶体管的硬掩模的蚀刻方法和结构
    • US07557000B2
    • 2009-07-07
    • US11609748
    • 2006-12-12
    • John ChenHanming WuDa Wei GaoBei ZhuPaolo Bonfanti
    • John ChenHanming WuDa Wei GaoBei ZhuPaolo Bonfanti
    • H01L21/8238
    • H01L29/7848H01L29/165H01L29/66628H01L29/66636Y10S438/938
    • A method for forming an strained silicon integrated circuit device. The method includes providing a semiconductor substrate and forming a dielectric layer overlying the semiconductor substrate. The method also includes forming a gate layer overlying the dielectric layer and forming a hard mask overlying the gate layer. The method patterns the gate layer to form a gate structure including edges using the hard mask as a protective layer. The method forms a dielectric layer overlying the gate structure to protect the gate structure including the edges. The method forms spacers from the dielectric layer, while maintaining the hard mask overlying the gate structure. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer and the hard mask as a protective layer, while the hard mask prevents any portion of the gate structure from being exposed. In a preferred embodiment, the method maintains the hard mask overlying the gate structure. The method includes depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region, while maintaining any portion of the gate layer from being exposed using the hard mask such that the gate structure is substantially free from any permanent deposition of silicon germanium material, which causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. In a preferred embodiment, the method removing the hard mask from the gate structure to expose a top portion of the gate structure and maintains the top portion of the gate structure being substantially free from any silicon germanium material.
    • 一种形成应变硅集成电路器件的方法。 该方法包括提供半导体衬底并形成覆盖半导体衬底的电介质层。 该方法还包括形成覆盖在电介质层上的栅极层,并形成覆盖栅极层的硬掩模。 该方法使栅极层形成包括使用硬掩模的边缘作为保护层的栅极结构。 该方法形成覆盖栅极结构的电介质层,以保护包括边缘的栅极结构。 该方法从电介质层形成间隔物,同时保持覆盖栅极结构的硬掩模。 该方法使用电介质层和硬掩模作为保护层来蚀刻与栅极结构相邻的源极区域和漏极区域,同时硬掩模防止栅极结构的任何部分暴露。 在优选实施例中,该方法保持覆盖栅极结构的硬掩模。 该方法包括将硅锗材料沉积到源极区域和漏极区域中以填充蚀刻的源极区域和蚀刻的漏极区域,同时保持栅极层的任何部分不被使用硬掩模曝光,使得栅极结构基本上是空的 来自硅锗材料的任何永久性沉积,其使得源极区域和漏极区域之间的沟道区域至少在形成于源极区域和漏极区域中的硅锗材料以压缩模式应变。 在优选实施例中,该方法从栅极结构去除硬掩模以露出栅极结构的顶部并且保持栅极结构的顶部基本上不含任何硅锗材料。
    • 35. 发明授权
    • Stage device
    • 舞台装置
    • US07257902B2
    • 2007-08-21
    • US11522400
    • 2006-09-18
    • Wei GaoSatoshi KiyonoYoshiyuki TomitaMakoto Tano
    • Wei GaoSatoshi KiyonoYoshiyuki TomitaMakoto Tano
    • G01D21/00
    • G03F7/70775G03F7/70716
    • This invention relates to a stage device which is moved with high accuracy in an X-Y direction and a rotating direction using a planar motor. The invention is aimed at reducing the size of the stage device and at performing accurately measurement of a position of the stage to the base. The stage device comprises a scale unit having a scale part on the entire plane of the base, and three two-dimensional angle sensors disposed on a bottom surface of a movable stage part. The scale unit and the two-dimensional angle sensors form a surface encode. A position of the movable stage part is measured by the surface encoder.
    • 本发明涉及一种使用平面电机在X-Y方向和旋转方向上高精度地移动的平台装置。 本发明的目的在于减小舞台装置的尺寸并且准确地测量舞台到底座的位置。 舞台装置包括在基座的整个平面上具有刻度部分的刻度单元,以及设置在可移动台部的底面上的三个二维角度传感器。 刻度单元和二维角度传感器形成表面编码。 可动平台部分的位置由表面编码器测量。
    • 38. 发明授权
    • Method of fabricating a p-type CaO-doped SrCu2O2 thin film
    • 制造p型CaO掺杂SrCu2O2薄膜的方法
    • US07087526B1
    • 2006-08-08
    • US11261020
    • 2005-10-27
    • Wei-Wei ZhuangWei GaoYoshi Ono
    • Wei-Wei ZhuangWei GaoYoshi Ono
    • H01L23/02
    • C23C26/00
    • A method of CaO-doped SrCu2O2 spin-on precursor synthesis and low temperature p-type thin film deposition, includes preparing a wafer to receive a spin-coating thereon; selecting metalorganic compounds to form a SrCu2O2 precursor, mixing and refluxing the metalorganic compounds to form a precursor mixture; filtering the precursor mixture to produce a spin-coating precursor; applying the spin-coating precursor to the wafer in a two-step spin coating procedure; baking the spin-coated wafer using a hot-plate bake to evaporate substantially all of the solvents; and annealing the spin-coated wafer to form a CaO-doped SrCu2O2 layer thereon.
    • 掺有CaO的SrCu 2 O 2 O 2旋涂前体合成和低温p型薄膜沉积的方法包括制备晶片以在其上接受旋涂法 ; 选择金属有机化合物以形成SrCu 2 O 2 O 2前体,将金属有机化合物混合并回流以形成前体混合物; 过滤前体混合物以产生旋涂前体; 以两步旋涂方法将旋涂前驱体施加到晶片上; 使用热板烘烤烘烤旋涂的晶片以基本上蒸发所有溶剂; 以及对旋涂的晶片退火以在其上形成掺杂CaO的SrCu 2 O 2 O 2层。