专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06873048B2 System and method for integrating multiple metal gates for CMOS applications 失效
标题翻译：用于集成多个金属栅极用于CMOS应用的系统和方法
公开(公告)号：US06873048B2
公开(公告)日：2005-03-29
申请号：US10376795
申请日：2003-02-27
申请人： Wei Gao , John F. Conley, Jr. , Yoshi Ono
发明人： Wei Gao , John F. Conley, Jr. , Yoshi Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78 , H01L23/48
CPC分类号： H01L29/66583 , H01L21/823842 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A dual-gate MOSFET with metal gates and a method for setting threshold voltage in such a MOSFET is provided. The method comprises: forming a gate oxide layer overlying first and second channel regions; forming a first metal layer having a first thickness overlying the gate oxide layer; forming a second metal layer having a second thickness overlying the first metal layer first thickness; selectively removing the second metal layer overlying the first channel region; forming a third metal layer; establishing a first MOSFET with a gate work function responsive to the thicknesses of the first and third metal layer overlying the first channel region; and, establishing a second MOSFET, complementary to the first MOSFET, with a gate work function responsive to the combination of the thicknesses of the first, second, and third metal layers overlying the second channel region.
摘要翻译：提供了具有金属栅极的双栅极MOSFET和用于设置这种MOSFET中的阈值电压的方法。该方法包括：形成覆盖第一和第二沟道区的栅极氧化层; 形成具有覆盖所述栅极氧化物层的第一厚度的第一金属层; 形成具有覆盖所述第一金属层第一厚度的第二厚度的第二金属层; 选择性地去除覆盖在第一沟道区上的第二金属层; 形成第三金属层; 建立具有响应于覆盖在第一沟道区上的第一和第三金属层的厚度的栅极功函数的第一MOSFET; 以及响应于覆盖在第二沟道区上的第一，第二和第三金属层的厚度的组合，建立与第一MOSFET互补的第二MOSFET。

2. 发明授权

US07473640B2 Reactive gate electrode conductive barrier 有权
标题翻译：无源栅电极导电屏障
公开(公告)号：US07473640B2
公开(公告)日：2009-01-06
申请号：US10784662
申请日：2004-02-23
申请人： John F. Conley, Jr. , Yoshi Ono , Wei Gao
发明人： John F. Conley, Jr. , Yoshi Ono , Wei Gao
IPC分类号： H01L29/72
CPC分类号： H01L21/28079 , H01L21/823842 , H01L29/4958
摘要： A method, and corresponding transistor structure are provided for protecting the gate electrode from an underlying gate insulator. The method comprises: forming a gate insulator overlying a channel region; forming a first metal barrier overlying the gate insulator, having a thickness of less than 5 nanometers (nm); forming a second metal gate electrode overlying the first metal barrier, having a thickness of greater than 10 nm; and, establishing a gate electrode work function exclusively responsive to the second metal. The second metal gate electrode can be one of the following materials: elementary metals such as p+ poly, n+ poly. Ta, W, Re, RuO2, Pt, Ti, Hf, Zr, Cu, V, Ir, Ni, Mn, Co, NbO, Pd, Mo, TaSiN, and Nb, and binary metals such as WN, TaN, and TiN. The first metal barrier can be a binary metal, such as TaN, TiN, or WN.
摘要翻译：提供了一种方法和相应的晶体管结构，用于保护栅极免受下层栅极绝缘体的影响。该方法包括：形成覆盖沟道区的栅极绝缘体; 形成覆盖栅极绝缘体的厚度小于5纳米（nm）的第一金属屏障; 形成覆盖所述第一金属屏障的第二金属栅电极，其厚度大于10nm; 并且建立专门响应于第二金属的栅电极功函数。第二金属栅电极可以是以下材料之一：元素金属，例如p + poly，n + poly。 Ta，W，Re，RuO 2，Pt，Ti，Hf，Zr，Cu，V，Ir，Ni，Mn，Co，NbO，Pd，Mo，TaSiN和Nb，二元金属如WN，TaN和TiN 。第一金属屏障可以是二元金属，例如TaN，TiN或WN。

3. 发明授权

US07029944B1 Methods of forming a microlens array over a substrate employing a CMP stop 失效
标题翻译：在使用CMP停止的衬底上形成微透镜阵列的方法
公开(公告)号：US07029944B1
公开(公告)日：2006-04-18
申请号：US10956789
申请日：2004-09-30
申请人： John F. Conley, Jr. , Yoshi Ono , Wei Gao , David R. Evans
发明人： John F. Conley, Jr. , Yoshi Ono , Wei Gao , David R. Evans
IPC分类号： H01L21/00
CPC分类号： H01L21/31053 , H01L21/31133 , H01L27/14627 , H01L27/14685
摘要： A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array. An embodiment of the method comprises providing a substrate having a surface with photo-elements on the surface; depositing a transparent material overlying the surface of the substrate; depositing a CMP stop overlying the transparent material; depositing a lens-shaping layer overlying the CMP stop layer; depositing and patterning a photoresist layer overlying the lens-shaping layer to form openings to expose the lens-shaping layer; introducing a first isotropic etchant into the openings and etching the lens-shaping layer where exposed to form initial lens shapes having a radius; stripping the photoresist; exposing the lens-shaping layer to a second isotropic etchant to increase the radius of the lens shapes; transferring the lens shape through the CMP stop layer into the transparent material using an anisotropic etch; and depositing a lens material overlying the transparent material, whereby the lens shapes are at least partially filled with lens material. Planarizing the lens material using CMP and stopping at the CMP stop layer.
摘要翻译：提供一种形成微透镜结构的方法以及采用微透镜阵列的CCD阵列结构。该方法的一个实施例包括提供具有在表面上具有光元件的表面的基底; 沉积覆盖衬底表面的透明材料; 沉积覆盖透明材料的CMP停止点; 沉积覆盖CMP停止层的透镜成形层; 沉积和图案化覆盖透镜成形层的光致抗蚀剂层以形成露出透镜成形层的开口; 在开口中引入第一各向同性蚀刻剂并蚀刻暴露于其中形成具有半径的初始透镜形状的透镜成形层; 剥离光刻胶; 将透镜成形层暴露于第二各向同性蚀刻剂以增加透镜形状的半径; 使用各向异性蚀刻将透镜形状通过CMP停止层转移到透明材料中; 以及沉积覆盖透明材料的透镜材料，由此透镜形状至少部分地被透镜材料填充。使用CMP对透镜材料进行平面化，并在CMP停止层处停止。

4. 发明授权

US07208768B2 Electroluminescent device 失效
标题翻译：电致发光器件
公开(公告)号：US07208768B2
公开(公告)日：2007-04-24
申请号：US10836669
申请日：2004-04-30
申请人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
发明人： Yoshi Ono , Wei Gao , John F. Conley, Jr. , Osamu Nishio , Keizo Sakiyama
IPC分类号： H01L27/15
CPC分类号： H01L33/28 , H01L33/18 , H01L33/34 , Y10S977/95
摘要： A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.
摘要翻译：提供了形成电致发光器件的方法。该方法包括：提供IV型半导体材料基板; 在衬底中形成p + / n +结，通常形成多个交错的p + / n +结; 并且形成覆盖衬底中的p + / n +结的电致发光层。 IV型半导体材料基板可以是Si，C，Ge，SiGe或SiC。例如，衬底可以是绝缘体上的硅（SOI），玻璃上的体积Si，Si或塑料上的Si。电致发光层可以是诸如纳米晶体Si，纳米晶体Ge，荧光聚合物或诸如ZnO，ZnS，ZnSe，CdSe和CdS的II-VI族材料的材料。在一些方面，所述方法还包括形成介于基片和电致发光层之间的绝缘膜。另一方面，该方法包括形成覆盖电致发光层的导电电极。

5. 发明授权

US07589464B2 Nanotip electrode electroluminescence device with contoured phosphor layer 失效
标题翻译：具有成像荧光粉层的纳米技术电极电致发光器件
公开(公告)号：US07589464B2
公开(公告)日：2009-09-15
申请号：US11070051
申请日：2005-03-01
申请人： John F. Conley, Jr. , David R. Evans , Wei Gao , Yoshi Ono
发明人： John F. Conley, Jr. , David R. Evans , Wei Gao , Yoshi Ono
IPC分类号： H05B33/26
CPC分类号： H05B33/10 , B82Y20/00 , C09K11/54 , C09K11/642 , H01L33/18 , H05B33/14
摘要： A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.
摘要翻译：提供了一种具有纳米尺度荧光体层的EL器件的器件和制造方法。该方法包括：形成具有纳米尖端的底部电极; 形成覆盖在底部电极上的荧光体层，具有不规则形状的顶部和底部表面; 并且形成覆盖磷光体层的顶部电极。底部电极顶表面具有纳米尖端轮廓，并且荧光体层不规则形状的顶表面和底表面具有与底部电极顶表面纳米尖端轮廓近似匹配的轮廓。在一个方面，在底部电极和荧光体层之间插入有轮廓的底部电介质，其具有顶部和底部表面，轮廓几乎与纳米尖端轮廓相匹配。类似地，顶部电介质可以插入在顶部电极和荧光体层之间，具有大致与荧光体层顶表面的轮廓相匹配的轮廓的底面。

6. 发明授权

US07462499B2 Carbon nanotube with ZnO asperities 失效
标题翻译：具有ZnO粗糙度的碳纳米管
公开(公告)号：US07462499B2
公开(公告)日：2008-12-09
申请号：US11262439
申请日：2005-10-28
申请人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
发明人： John F. Conley, Jr. , Yoshi Ono , Lisa H. Stecker , Sheng Teng Hsu , Josh M. Green , Lifeng Dong , Jun Jiao
IPC分类号： H01L21/00
CPC分类号： H01J9/025 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/162 , C01B32/168 , C01B2202/34 , C01B2202/36 , H01J1/304 , H01J2201/30469 , H01L21/0237 , H01L21/02381 , H01L21/02444 , H01L21/02472 , H01L21/02483 , H01L21/02513 , H01L21/02554 , H01L21/02601 , Y10S977/754
摘要： A ZnO asperity-covered carbon nanotube (CNT) device has been provided, along with a corresponding fabrication method. The method comprises: forming a substrate; growing CNTs from the substrate; conformally coating the CNTs with ZnO; annealing the ZnO-coated CNTs; and, forming ZnO asperities on the surface of the CNTs in response to the annealing. In one aspect, the ZnO asperities have a density in the range of about 100 to 1000 ZnO asperities per CNT. The density is dependent upon the deposited ZnO film thickness and annealing parameters. The CNTs are conformally coating with ZnO using a sputtering, chemical vapor deposition (CVD), spin-on, or atomic layer deposition (ALD). For example, an ALD process can be to deposit a layer of ZnO over the CNTs having a thickness in the range of 1.2 to 200 nanometers (nm).
摘要翻译：已经提供了ZnO微粒覆盖碳纳米管（CNT）器件，以及相应的制造方法。该方法包括：形成衬底; 从底物生长CNT; 用ZnO共形涂覆CNT; 退火ZnO涂层的CNT; 并且响应于退火在CNT的表面上形成ZnO粗糙度。在一个方面，ZnO粗糙度的密度在每个CNT约100-1000nm的ZnO粗糙度的范围内。密度取决于沉积的ZnO膜厚度和退火参数。使用溅射，化学气相沉积（CVD），旋涂或原子层沉积（ALD），使用ZnO共形涂覆CNT。例如，ALD工艺可以在厚度在1.2至200纳米（nm）范围内的CNT上沉积ZnO层。

7. 发明授权

US07528695B2 Method to manipulate selectivity of a metal oxide sensor 失效
标题翻译：操纵金属氧化物传感器选择性的方法
公开(公告)号：US07528695B2
公开(公告)日：2009-05-05
申请号：US11361519
申请日：2006-02-23
申请人： John F. Conley, Jr. , Yoshi Ono
发明人： John F. Conley, Jr. , Yoshi Ono
IPC分类号： H01C7/00
CPC分类号： G01N33/0027
摘要： A method of selectively enhancing the sensitivity of a metal oxide sensor includes fabricating a ZnO sensor having a ZnO sensor element therein; and exposing the ZnO sensor element to a plasma stream.
摘要翻译：选择性提高金属氧化物传感器的灵敏度的方法包括制造其中具有ZnO传感器元件的ZnO传感器; 并将ZnO传感器元件暴露于等离子体流。

8. 发明授权

US07160819B2 Method to perform selective atomic layer deposition of zinc oxide 有权
标题翻译：执行氧化锌选择性原子层沉积的方法
公开(公告)号：US07160819B2
公开(公告)日：2007-01-09
申请号：US11114862
申请日：2005-04-25
申请人： John F. Conley, Jr. , Yoshi Ono , David R. Evans
发明人： John F. Conley, Jr. , Yoshi Ono , David R. Evans
IPC分类号： H01L21/31
CPC分类号： H01L21/0228 , C23C16/042 , C23C16/407 , C23C16/45525 , H01L21/0217 , H01L21/02175 , H01L21/02334 , H01L21/0234 , H01L21/3141
摘要： A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H2O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.
摘要翻译：在准备硅晶片的晶片上的ZnO的选择性ALD的方法; 在其中要抑制ZnO沉积的选定区域中用封闭剂对硅晶片进行图案化，其中封闭剂取自一组封闭剂，包括异丙醇，丙酮和去离子水; 在约140℃至170℃的温度下，使用二乙基锌和H 2 O 2，通过ALD在晶片上沉积ZnO层。并从晶片上除去封闭剂。

9. 发明授权

US06686212B1 Method to deposit a stacked high-&kgr; gate dielectric for CMOS applications 有权
标题翻译：沉积用于CMOS应用的堆叠的高kappa栅极电介质的方法
公开(公告)号：US06686212B1
公开(公告)日：2004-02-03
申请号：US10286100
申请日：2002-10-31
申请人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
发明人： John F. Conley, Jr. , Yoshi Ono , Rajendra Solanki
IPC分类号： H01L2100
CPC分类号： H01L21/28194 , C23C16/405 , C23C16/45529 , H01L21/3141 , H01L21/31604 , H01L21/31683 , H01L21/823857 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： A method of forming a layer of high-&kgr; dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.
摘要翻译：在集成电路中形成高k电介质材料层的方法包括制备硅衬底; 使用ALD与金属硝酸盐前体沉积第一层金属氧化物; 使用ALD与金属氯化物前体沉积另一层金属氧化物; 并完成集成电路。

10. 发明授权

US07442415B2 Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films 有权
标题翻译：高介电常数薄膜原子层沉积（ALD）的调制温度法
公开(公告)号：US07442415B2
公开(公告)日：2008-10-28
申请号：US10412550
申请日：2003-04-11
申请人： John F. Conley, Jr. , Yoshi Ono , Gregory M. Stecker
发明人： John F. Conley, Jr. , Yoshi Ono , Gregory M. Stecker
IPC分类号： C23C16/00
CPC分类号： H01L21/0228 , C23C16/45527 , C23C16/56 , H01L21/02181 , H01L21/02205 , H01L21/02318 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31637 , H01L21/31641 , H01L21/31645
摘要： A method of forming a layer of high-k dielectric material in an integrated circuit includes preparing a silicon substrate; forming a high-k dielectric layer by a sequence of ALD cycles including: depositing a first layer of metal ligand using ALD with an oxygen-containing first precursor; and depositing a second layer of metal ligand using ALD with a second precursor; repeating the sequence of ALD cycles N times until a near-critical thickness of metal oxide is formed; annealing the substrate and metal oxide layers every N ALD cycles in an elevated temperature anneal; repeating the sequence of ALD cycles and elevated temperature anneals until a high-k dielectric layer of desired thickness is formed; annealing the substrate and the metal oxide layers in a final annealing step; and completing the integrated circuit.
摘要翻译：在集成电路中形成高k介电材料层的方法包括制备硅衬底; 通过一系列ALD循环形成高k电介质层，包括：使用ALD与含氧第一前体沉积第一层金属配体; 以及使用ALD与第二前体沉积第二层金属配体; 重复ALD循环序列N次，直到形成近临界厚度的金属氧化物; 在高温退火中每N个ALD循环退火衬底和金属氧化物层; 重复ALD循环的序列和升高的温度退火直到形成所需厚度的高k电介质层; 在最终退火步骤中退火衬底和金属氧化物层; 并完成集成电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式