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31. 发明授权

US06920512B2 Computer architecture and system for efficient management of bi-directional bus 有权
标题翻译：用于双向总线高效管理的计算机架构和系统
公开(公告)号：US06920512B2
公开(公告)日：2005-07-19
申请号：US10780395
申请日：2004-02-17
申请人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
发明人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4059
摘要： An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular, by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
摘要翻译：一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。特别地，通过智能地管理双向总线上的读取和写入，可以减少总线延迟，同时仍然确保没有总线争用或读取/写入饥饿。这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

32. 发明授权

US06662265B1 Mechanism to track all open pages in a DRAM memory system 有权
标题翻译：跟踪DRAM存储器系统中所有打开的页面的机制
公开(公告)号：US06662265B1
公开(公告)日：2003-12-09
申请号：US09652704
申请日：2000-08-31
申请人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
发明人： Richard E. Kessler , Maurice B. Steinman , Michael S. Bertone , Peter J. Bannon , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A system and method is disclosed to track a large number of open pages in a computer memory system. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. A RIMM module containing RDRAM devices is coupled to each processor, each RDRAM containing a plurality of memory banks. The page table increases system memory performance by tracking a large number of open memory pages. Associated with the page table is a bank active table that indicates the memory banks in each RDRAM device having open memory pages. The page table enqueues accesses to the RIMM module in a precharge queue resulting from a page miss caused by the address of an open memory page occupying the same row of the page table as the address of the system memory access resulting in the page miss. The page table also enqueues accesses to system memory in a Row-address-select (“RAS”) queue resulting from a page miss caused by a row of the page table not containing any open memory page address. The page table enqueues accesses to system memory resulting in page hits to open memory pages in a Column-address-select (“CAS”) queue. An entry in the precharge queue is then enqueued into the RAS queue. An entry in the RAS queue after completion is enqueued into the CAS Read or CAS Write queue.
摘要翻译：公开了一种在计算机存储器系统中跟踪大量打开页面的系统和方法。计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。包含RDRAM设备的RIMM模块耦合到每个处理器，每个RDRAM包含多个存储器组。页面表通过跟踪大量的开放内存页面来增加系统内存性能。与页表相关联的是一个存储区活动表，指示每个具有打开存储器页的RDRAM设备中的存储体。页表格排队访问预充电队列中的RIMM模块，这是由于打开的内存页面的地址与页表的同一行的地址导致的页错误导致的系统内存访问的地址导致页错过。页表还对由行页地址选择（“RAS”）队列访问系统内存进行排队，这是由于不包含任何打开的内存页地址的页表的行引起的页错误导致的。页面表格对对系统内存的访问进行排队，导致页面命中，以打开列地址选择（“CAS”）队列中的内存页面。然后将预充电队列中的条目排入RAS队列。完成后RAS队列中的条目排入CAS读取或CAS写入队列。

33. 发明授权

US06591349B1 Mechanism to reorder memory read and write transactions for reduced latency and increased bandwidth 失效
标题翻译：重新排序内存读取和写入事务的机制，以减少延迟和增加的带宽
公开(公告)号：US06591349B1
公开(公告)日：2003-07-08
申请号：US09653094
申请日：2000-08-31
申请人： Maurice B. Steinman , Gregg A. Bouchard
发明人： Maurice B. Steinman , Gregg A. Bouchard
IPC分类号： G06F1200
CPC分类号： G06F13/1642 , G06F13/1631
摘要： A system and method is disclosed to increase computer memory system performance by reducing lost clock cycles caused by bus turnarounds. The computer system contains one or more processors each including a memory controller containing a page table, the page table organized into a plurality of rows with each row able to store an address of an open memory page. The memory controller also contains a precharge queue, a Row-address-select (“RAS”) queue, a Column-address-select (“CAS”) Read queue, and a CAS Write queue. The CAS Read queue and CAS Write queue outputs are connected to a 2-to-1 multiplexer. The 2-to-1 multiplexer streams groups of read requests and groups of write requests to main memory resulting in fewer lost clock cycles caused by bus turnarounds. The memory controller places system memory read requests into the CAS Read queue and system memory write requests into the CAS Write queue.
摘要翻译：公开了一种通过减少由总线周转引起的丢失的时钟周期来增加计算机存储器系统性能的系统和方法。计算机系统包含一个或多个处理器，每个处理器包括包含页表的存储器控制器，所述页表被组织成多行，每行能够存储打开存储器页的地址。存储器控制器还包含预充电队列，行地址选择（“RAS”）队列，列地址选择（“CAS”）读队列和CAS写队列。 CAS读队列和CAS写队列输出连接到2对1多路复用器。 2对1多路复用器将读请求组和写请求组传送到主存储器，导致由总线周转引起的丢失时钟周期更少。内存控制器将系统内存读取请求放入CAS读取队列和系统内存写入请求到CAS写队列中。

34. 发明授权

US5559987A Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system 失效
标题翻译：用于在基于总线协议的计算机系统中更新重复标签状态的方法和装置
公开(公告)号：US5559987A
公开(公告)日：1996-09-24
申请号：US268409
申请日：1994-06-30
申请人： Denis Foley , Maurice B. Steinman , Stephen R. VanDoren
发明人： Denis Foley , Maurice B. Steinman , Stephen R. VanDoren
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.
摘要翻译：用于更新重复标签缓存状态信息的计算机系统中的方法和装置。本发明在具有耦合到根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块的计算机系统中操作。用于修改处理器的重复标签状态信息条目的处理器命令和地址由处理器提供给其到系统总线的地址接口。系统总线命令和地址信息被接收并存储在地址接口的接口管道中。确定接口管道中的系统总线命令和地址是否有效。如果接口流水线中没有有效的系统总线命令和地址，则不会确定处理器命令和地址是否与系统总线命令和地址冲突，从而更新重复标签状态信息。

35. 发明授权

US08862920B2 Power state management of an input/output servicing component of a processor system 有权
标题翻译：处理器系统的输入/输出服务组件的电源状态管理
公开(公告)号：US08862920B2
公开(公告)日：2014-10-14
申请号：US13162425
申请日：2011-06-16
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3253 , G06F1/3275 , Y02D10/14 , Y02D10/151
摘要： A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.
摘要翻译：调节处理系统中的功率状态的方法可以从将当前处理器功率状态报告给输入 - 输出集线器的处理器组件开始，其中当前处理器功率状态对应于多个不同的处理器功率状态中的一个，状态为非活动状态。输入 - 输出集线器接收指示当前处理器功率状态的数据，并且响应于接收到当前处理器功率状态，建立对应于多个不同集线器功率状态中的一个的最低可允许集线器功率状态，该状态从活动状态到非活动状态。该方法通过确定用于输入 - 输出集线器的当前集线器功率状态来继续，其中当前集线器功率状态的深度小于或等于最低可允许集线器功率状态的深度。

36. 发明授权

US08112647B2 Protocol for power state determination and demotion 有权
标题翻译：电力状态决定和降级议定书
公开(公告)号：US08112647B2
公开(公告)日：2012-02-07
申请号：US12254650
申请日：2008-10-20
申请人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
发明人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.
摘要翻译：系统可以包括多个处理单元，以及与处理单元接口的控制单元和监控单元。控制单元可以接收将处理单元转换到各个目标功率状态的请求，并且指定与各个目标功率状态相对应的各个目标HW功率状态。监视单元可以监视系统的操作特性，并且基于操作特性确定是否允许处理单元转换到相应的目标硬件（HW）功率状态。控制单元可以被配置为针对确定不应该允许转换到其各自的目标HW功率状态的每个处理单元，将相应的目标HW功率状态改变到相应的更新的HW功率状态。控制单元还可以被配置为当多个处理的子集的处理单元时，基于多个处理单元的子集的处理单元的各个目标HW功率状态来推断公共目标HW功率状态单位共享至少一个资源域。

37. 发明申请

US20110112798A1 CONTROLLING PERFORMANCE/POWER BY FREQUENCY CONTROL OF THE RESPONDING NODE 审中-公开
标题翻译：通过响应节点的频率控制来控制性能/功率
公开(公告)号：US20110112798A1
公开(公告)日：2011-05-12
申请号：US12623997
申请日：2009-11-23
申请人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
发明人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
IPC分类号： G21C17/00
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.
摘要翻译：处理节点跟踪与其内部缓存或存储器系统相关联的探测活动级别。如果探测器活动级别增加到阈值探测器活动级别以上，则处理节点的性能状态将增加到其当前的性能状态以提供增强的响应探测请求的性能能力。响应于探测器活动级别高于阈值探测器活动级别而进入更高性能状态之后，处理节点响应于探测活动的减少而返回到较低的性能状态。可能存在多个阈值探测活动级别和相关的性能状态。

38. 发明申请

US20110078478A1 METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY 有权
标题翻译：基于活动请求频率的功率状态之间的设备转换方法和装置
公开(公告)号：US20110078478A1
公开(公告)日：2011-03-31
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

39. 发明申请

US20100162256A1 OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP 审中-公开
标题翻译：优化芯片集成系统中的应用功耗和性能
公开(公告)号：US20100162256A1
公开(公告)日：2010-06-24
申请号：US12338459
申请日：2008-12-18
申请人： Alexander Branover , Helmut W. Prengel , Anthony Asaro , Sebastian Nussbaum , Maurice B. Steinman
发明人： Alexander Branover , Helmut W. Prengel , Anthony Asaro , Sebastian Nussbaum , Maurice B. Steinman
IPC分类号： G06F9/46
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.
摘要翻译：一种用于确定共享资源的操作点的方法。该方法包括从多个功能单元中的每一个接收对共享资源的访问需求的指示，并且基于它们各自的指示确定多个功能单元中的最大访问需求。该方法还包括基于最大访问需求来确定共享资源的所需工作点，其中共享资源由多个功能单元中的每个功能单元共享，将所需的操作点与共享资源的当前工作点进行比较，并且如果所需和当前的操作点不同，则从当前操作点改变到所需的操作点。

40. 发明授权

US06704817B1 Computer architecture and system for efficient management of bi-directional bus 有权
标题翻译：用于双向总线高效管理的计算机架构和系统
公开(公告)号：US06704817B1
公开(公告)日：2004-03-09
申请号：US09652323
申请日：2000-08-31
申请人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
发明人： Maurice B. Steinman , Richard E. Kessler , Gregg A. Bouchard
IPC分类号： G06F1300
CPC分类号： G06F13/4059
摘要： An efficient system and method for managing reads and writes on a bi-directional bus to optimize bus performance while avoiding bus contention and avoiding read/write starvation. In particular by intelligently managing reads and writes on a bi-directional bus, bus latency can be reduced while still ensuring no bus contention or read/write starvation. This is accomplished by utilizing bus streaming control logic, separate queues for reads and writes, and a simple 2 to 1 mux.
摘要翻译：一种有效的系统和方法，用于管理双向总线上的读取和写入，以优化总线性能，同时避免总线争用并避免读取/写入饥饿。特别是通过智能地管理双向总线上的读写操作，可以减少总线延迟，同时确保没有总线争用或读/写饥饿。这是通过利用总线流控制逻辑，单独的队列读取和写入以及简单的2到1多路复用来实现的。

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