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1. 发明授权

US08112647B2 Protocol for power state determination and demotion 有权
标题翻译：电力状态决定和降级议定书
公开(公告)号：US08112647B2
公开(公告)日：2012-02-07
申请号：US12254650
申请日：2008-10-20
申请人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
发明人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.
摘要翻译：系统可以包括多个处理单元，以及与处理单元接口的控制单元和监控单元。控制单元可以接收将处理单元转换到各个目标功率状态的请求，并且指定与各个目标功率状态相对应的各个目标HW功率状态。监视单元可以监视系统的操作特性，并且基于操作特性确定是否允许处理单元转换到相应的目标硬件（HW）功率状态。控制单元可以被配置为针对确定不应该允许转换到其各自的目标HW功率状态的每个处理单元，将相应的目标HW功率状态改变到相应的更新的HW功率状态。控制单元还可以被配置为当多个处理的子集的处理单元时，基于多个处理单元的子集的处理单元的各个目标HW功率状态来推断公共目标HW功率状态单位共享至少一个资源域。

2. 发明申请

US20100058078A1 Protocol for Power State Determination and Demotion 有权
标题翻译：权力状态决定和降级议定书
公开(公告)号：US20100058078A1
公开(公告)日：2010-03-04
申请号：US12254650
申请日：2008-10-20
申请人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
发明人： Alexander Branover , Frank P. Helms , John P. Petry , Maurice B. Steinman
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.
摘要翻译：系统可以包括多个处理单元，以及与处理单元接口的控制单元和监控单元。控制单元可以接收将处理单元转换到各个目标功率状态的请求，并且指定与各个目标功率状态相对应的各个目标HW功率状态。监视单元可以监视系统的操作特性，并且基于操作特性确定是否允许处理单元转换到相应的目标硬件（HW）功率状态。控制单元可以被配置为针对确定不应该允许转换到其各自的目标HW功率状态的每个处理单元，将相应的目标HW功率状态改变到相应的更新的HW功率状态。控制单元还可以被配置为当多个处理的子集的处理单元时，基于多个处理单元的子集的处理单元的各个目标HW功率状态来推断公共目标HW功率状态单位共享至少一个资源域。

3. 发明授权

US08966305B2 Managing processor-state transitions 有权
标题翻译：管理处理器状态转换
公开(公告)号：US08966305B2
公开(公告)日：2015-02-24
申请号：US13174144
申请日：2011-06-30
申请人： Alexander Branover , Maurice B. Steinman , John P. Petry
发明人： Alexander Branover , Maurice B. Steinman , John P. Petry
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3203
摘要： Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.
摘要翻译：公开了关于管理空闲功率状态的进入和退出的功耗和延迟的技术。在一个实施例中，处理器包括被配置为在包括操作功率状态和至少一个空闲功率状态的多个功率状态（例如，C状态）中操作的处理核心。处理核心还被配置为在多个执行状态下操作。处理器还包括功率管理单元，其被配置为从处理核心接收进入至少一个空闲功率状态的请求。功率管理单元被配置为基于所请求的空闲功率状态来选择多个性能状态中的第一个（例如，P状态）。在一个实施例中，功率管理单元还被配置为使得处理核心在进入所请求的空闲功率状态之前转变到所选择的第一执行状态。

4. 发明申请

US20130007494A1 MANAGING PROCESSOR-STATE TRANSITIONS 有权
标题翻译：管理处理器状态转换
公开(公告)号：US20130007494A1
公开(公告)日：2013-01-03
申请号：US13174144
申请日：2011-06-30
申请人： Alexander Branover , Maurice B. Steinman , John P. Petry
发明人： Alexander Branover , Maurice B. Steinman , John P. Petry
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.
摘要翻译：公开了关于管理空闲功率状态的进入和退出的功耗和延迟的技术。在一个实施例中，处理器包括被配置为在包括操作功率状态和至少一个空闲功率状态的多个功率状态（例如，C状态）中操作的处理核心。处理核心还被配置为在多个执行状态下操作。处理器还包括功率管理单元，其被配置为从处理核心接收进入至少一个空闲功率状态的请求。功率管理单元被配置为基于所请求的空闲功率状态来选择多个性能状态中的第一个（例如，P状态）。在一个实施例中，功率管理单元还被配置为使得处理核心在进入所请求的空闲功率状态之前转变到所选择的第一执行状态。

5. 发明授权

US08566628B2 North-bridge to south-bridge protocol for placing processor in low power state 有权
标题翻译：用于将处理器置于低功率状态的北桥南桥协议
公开(公告)号：US08566628B2
公开(公告)日：2013-10-22
申请号：US12436439
申请日：2009-05-06
申请人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
发明人： Alexander Branover , Maurice B. Steinman , Ming L. So , Xiao Gang Zheng
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3253 , Y02D10/151
摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.
摘要翻译：处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。北桥还从南桥集成电路获得了第二个功率状态建议。北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

6. 发明授权

US08862920B2 Power state management of an input/output servicing component of a processor system 有权
标题翻译：处理器系统的输入/输出服务组件的电源状态管理
公开(公告)号：US08862920B2
公开(公告)日：2014-10-14
申请号：US13162425
申请日：2011-06-16
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/3253 , G06F1/3275 , Y02D10/14 , Y02D10/151
摘要： A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.
摘要翻译：调节处理系统中的功率状态的方法可以从将当前处理器功率状态报告给输入 - 输出集线器的处理器组件开始，其中当前处理器功率状态对应于多个不同的处理器功率状态中的一个，状态为非活动状态。输入 - 输出集线器接收指示当前处理器功率状态的数据，并且响应于接收到当前处理器功率状态，建立对应于多个不同集线器功率状态中的一个的最低可允许集线器功率状态，该状态从活动状态到非活动状态。该方法通过确定用于输入 - 输出集线器的当前集线器功率状态来继续，其中当前集线器功率状态的深度小于或等于最低可允许集线器功率状态的深度。

7. 发明申请

US20110112798A1 CONTROLLING PERFORMANCE/POWER BY FREQUENCY CONTROL OF THE RESPONDING NODE 审中-公开
标题翻译：通过响应节点的频率控制来控制性能/功率
公开(公告)号：US20110112798A1
公开(公告)日：2011-05-12
申请号：US12623997
申请日：2009-11-23
申请人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
发明人： Alexander Branover , Maurice B. Steinman , Jonathan D. Hauke , Jonathan M. Owen
IPC分类号： G21C17/00
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.
摘要翻译：处理节点跟踪与其内部缓存或存储器系统相关联的探测活动级别。如果探测器活动级别增加到阈值探测器活动级别以上，则处理节点的性能状态将增加到其当前的性能状态以提供增强的响应探测请求的性能能力。响应于探测器活动级别高于阈值探测器活动级别而进入更高性能状态之后，处理节点响应于探测活动的减少而返回到较低的性能状态。可能存在多个阈值探测活动级别和相关的性能状态。

8. 发明申请

US20110078478A1 METHOD AND APPARATUS FOR TRANSITIONING DEVICES BETWEEN POWER STATES BASED ON ACTIVITY REQUEST FREQUENCY 有权
标题翻译：基于活动请求频率的功率状态之间的设备转换方法和装置
公开(公告)号：US20110078478A1
公开(公告)日：2011-03-31
申请号：US12566930
申请日：2009-09-25
申请人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
发明人： Alexander Branover , Denis Rystsov , Maurice B. Steinman , Jonathan M. Owen , Denis J. Foley
IPC分类号： G06F1/32 , G05F1/10
CPC分类号： G06F1/3203 , Y02D10/126
摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.
摘要翻译：用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

9. 发明申请

US20100162256A1 OPTIMIZATION OF APPLICATION POWER CONSUMPTION AND PERFORMANCE IN AN INTEGRATED SYSTEM ON A CHIP 审中-公开
标题翻译：优化芯片集成系统中的应用功耗和性能
公开(公告)号：US20100162256A1
公开(公告)日：2010-06-24
申请号：US12338459
申请日：2008-12-18
申请人： Alexander Branover , Helmut W. Prengel , Anthony Asaro , Sebastian Nussbaum , Maurice B. Steinman
发明人： Alexander Branover , Helmut W. Prengel , Anthony Asaro , Sebastian Nussbaum , Maurice B. Steinman
IPC分类号： G06F9/46
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.
摘要翻译：一种用于确定共享资源的操作点的方法。该方法包括从多个功能单元中的每一个接收对共享资源的访问需求的指示，并且基于它们各自的指示确定多个功能单元中的最大访问需求。该方法还包括基于最大访问需求来确定共享资源的所需工作点，其中共享资源由多个功能单元中的每个功能单元共享，将所需的操作点与共享资源的当前工作点进行比较，并且如果所需和当前的操作点不同，则从当前操作点改变到所需的操作点。

10. 发明授权

US09021209B2 Cache flush based on idle prediction and probe activity level 有权
标题翻译：基于空闲预测和探测活动级别的缓存刷新
公开(公告)号：US09021209B2
公开(公告)日：2015-04-28
申请号：US12702085
申请日：2010-02-08
申请人： Alexander Branover , Maurice B. Steinman
发明人： Alexander Branover , Maurice B. Steinman
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F1/3203 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.
摘要翻译：处理节点跟踪与其高速缓存相关联的探测活动级别。处理节点和/或处理系统进一步预测空闲持续时间。如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到高于其当前性能状态，以提供响应探测请求的增强的性能能力。

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