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1. 发明授权

US6154816A Low occupancy protocol for managing concurrent transactions with dependencies 失效
标题翻译：用于管理具有依赖关系的并发事务的低占用协议
公开(公告)号：US6154816A
公开(公告)日：2000-11-28
申请号：US957565
申请日：1997-10-24
申请人： Simon C. Steely , Madhumitra Sharma , Stephen R. VanDoren
发明人： Simon C. Steely , Madhumitra Sharma , Stephen R. VanDoren
IPC分类号： G06F9/46 , G06F12/08 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52 , G06F12/0813 , G06F12/0828
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

2. 发明授权

US6014690A Employing multiple channels for deadlock avoidance in a cache coherency protocol 失效
标题翻译：在缓存一致性协议中使用多个通道来实现死锁避免
公开(公告)号：US6014690A
公开(公告)日：2000-01-11
申请号：US957531
申请日：1997-10-24
申请人： Stephen R. VanDoren , Madhumitra Sharma , Simon C. Steely
发明人： Stephen R. VanDoren , Madhumitra Sharma , Simon C. Steely
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0828 , G06F12/0813 , G06F12/0817
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

3. 发明授权

US06279084B1 Shadow commands to optimize sequencing of requests in a switch-based multi-processor system 失效
标题翻译：影子命令来优化基于交换机的多处理器系统中的请求排序
公开(公告)号：US06279084B1
公开(公告)日：2001-08-21
申请号：US08957062
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Hari Krishnan Nagpal
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Hari Krishnan Nagpal
IPC分类号： G06F1300
CPC分类号： G06F13/161 , G06F12/0826
摘要： The invention pertains to serializing local and remote references to a portion of a shared memory to optimize sequencing of requests in a switch-based, multi-processor system in which the local and remote references can occur concurrently. Usually, local accesses are typically much faster than remote accesses. Thus, in the interest of performance, both local and remote accesses are permitted to occur concurrently in the multiprocessing system. However, in one instance a local access can cause deadlock problems for a remote access. In addition, problems associated with coherency of the shared memory can also arise. Thus, in order to prevent deadlock problems and to maintain coherency of a shared memory, if a local reference to an address of memory has been forwarded to a switch, in this instance a hierarchical switch, then all subsequent references to that address of memory are forwarded to the hierarchical switch. The hierarchical switch has ordering properties that maintain the received order of inputs.
摘要翻译：本发明涉及将本地和远程引用的序列化到共享存储器的一部分，以优化基于交换机的多处理器系统中的请求的排序，其中本地和远程引用可以同时发生。通常，本地访问通常比远程访问快得多。因此，为了表现，本地和远程访问允许在多处理系统中同时发生。但是，在一个实例中，本地访问可能会导致远程访问的死锁问题。此外，还可能出现与共享存储器的一致性相关的问题。因此，为了防止死锁问题并保持共享存储器的一致性，如果对存储器的地址的本地引用已被转发到交换机，则在这种情况下是分层交换机，则所有后续对存储器地址的引用是转发到分层交换机。分层交换机具有维持接收的输入顺序的排序属性。

4. 发明授权

US6122714A Order supporting mechanisms for use in a switch-based multi-processor system 失效
标题翻译：用于基于交换机的多处理器系统中的订单支持机制
公开(公告)号：US6122714A
公开(公告)日：2000-09-19
申请号：US957298
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , David M. Fenwick
IPC分类号： G06F12/08 , G06F9/46 , G06F15/167 , G06F12/16
CPC分类号： G06F9/52
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

5. 发明授权

US6101420A Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories 失效
标题翻译：在具有粗略目录的基于交换机的多处理系统中消除歧义指令的方法和装置
公开(公告)号：US6101420A
公开(公告)日：2000-08-08
申请号：US957543
申请日：1997-10-24
申请人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Kourosh Gharachorloo
发明人： Stephen R. VanDoren , Simon C. Steely , Madhumitra Sharma , Kourosh Gharachorloo
IPC分类号： G05B19/18
CPC分类号： G05B19/0421 , G05B2219/2213 , G05B2219/2227
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

6. 发明授权

US5638538A Turbotable: apparatus for directing address and commands between multiple consumers on a node coupled to a pipelined system bus 失效
标题翻译：可触发的：用于在耦合到流水线系统总线的节点上的多个消费者之间指导地址和命令的装置
公开(公告)号：US5638538A
公开(公告)日：1997-06-10
申请号：US372533
申请日：1995-01-13
申请人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
发明人： Stephen R. VanDoren , Denis J. Foley , Maurice B. Steinman
IPC分类号： G06F13/36 , G06F13/00 , G06F12/00
CPC分类号： G06F13/36
摘要： A command queueing apparatus for directing address and command information amongst the various interfaces, or consumers, on a multi-CPU node in a computer system. The apparatus includes a core queue containing core queue entries, each core queue entry corresponding to a pending system bus operation. Each core queue entry includes one or more consumer information fields specific to each consumer. Also included is a plurality of virtual queues, each virtual queue corresponding to a consumer, each virtual queue having a virtual queue entry. A virtual queue entry for a consumer is a subset of the fields of a core queue entry, the subset of fields including the consumer information fields for the consumer corresponding to the virtual queue.
摘要翻译：一种用于在计算机系统中的多CPU节点上指导各种接口或消费者之间的地址和命令信息的命令排队装置。该装置包括一个包含核心队列条目的核心队列，每个核心队列条目对应于待处理的系统总线操作。每个核心队列条目包括每个消费者特有的一个或多个消费者信息字段。还包括多个虚拟队列，每个虚拟队列对应于消费者，每个虚拟队列具有虚拟队列条目。消费者的虚拟队列条目是核心队列条目的字段的子集，字段的子集包括与虚拟队列对应的消费者的消费者信息字段。

7. 发明授权

US6108752A Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency 失效
标题翻译：用于在基于交换机的多处理器系统中延迟受害者写入以维持数据一致性的方法和装置
公开(公告)号：US6108752A
公开(公告)日：2000-08-22
申请号：US957566
申请日：1997-10-24
申请人： Stephen R. VanDoren , Paul M. Goodwin
发明人： Stephen R. VanDoren , Paul M. Goodwin
IPC分类号： G06F12/08
CPC分类号： G06F12/0813
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

8. 发明授权

US5559987A Method and apparatus for updating a duplicate tag status in a snoop bus protocol based computer system 失效
标题翻译：用于在基于总线协议的计算机系统中更新重复标签状态的方法和装置
公开(公告)号：US5559987A
公开(公告)日：1996-09-24
申请号：US268409
申请日：1994-06-30
申请人： Denis Foley , Maurice B. Steinman , Stephen R. VanDoren
发明人： Denis Foley , Maurice B. Steinman , Stephen R. VanDoren
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.
摘要翻译：用于更新重复标签缓存状态信息的计算机系统中的方法和装置。本发明在具有耦合到根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块的计算机系统中操作。用于修改处理器的重复标签状态信息条目的处理器命令和地址由处理器提供给其到系统总线的地址接口。系统总线命令和地址信息被接收并存储在地址接口的接口管道中。确定接口管道中的系统总线命令和地址是否有效。如果接口流水线中没有有效的系统总线命令和地址，则不会确定处理器命令和地址是否与系统总线命令和地址冲突，从而更新重复标签状态信息。

9. 发明授权

US06249520B1 High-performance non-blocking switch with multiple channel ordering constraints 失效
标题翻译：具有多通道排序限制的高性能非阻塞开关
公开(公告)号：US06249520B1
公开(公告)日：2001-06-19
申请号：US08957664
申请日：1997-10-24
申请人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
发明人： Simon C. Steely, Jr. , Stephen R. VanDoren , Madhumitra Sharma , Craig D. Keefer , David W. Davis
IPC分类号： H04L1250
CPC分类号： G06F13/4022 , G06F12/0826 , G06F15/17393
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

10. 发明授权

US6085276A Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies 失效
标题翻译：具有数据交换机的多处理器计算机系统具有用于消除仲裁相互依赖性的同时插入缓冲器
公开(公告)号：US6085276A
公开(公告)日：2000-07-04
申请号：US957751
申请日：1997-10-24
申请人： Stephen R. VanDoren , Madhumitra Sharma
发明人： Stephen R. VanDoren , Madhumitra Sharma
IPC分类号： G06F13/362 , G06F13/40 , G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.
摘要翻译：用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。

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