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1. 发明授权

US08156317B2 Integrated circuit with secure boot from a debug access port and method therefor 有权
标题翻译：具有来自调试接入端口的安全引导的集成电路及其方法
公开(公告)号：US08156317B2
公开(公告)日：2012-04-10
申请号：US12122484
申请日：2008-05-16
申请人： James Lyall Esliger , Denis Foley
发明人： James Lyall Esliger , Denis Foley
IPC分类号： G06F15/177
CPC分类号： G06F21/572 , G06F21/575
摘要： An integrated circuit (100) may receive a boot loader code (114) via a debug access port (105), wherein a boot logic is operative to block, upon a reset (123) of the programmable processor (103) from the debug access port (105), commands and to the programmable processor from the debug access port, while still allowing the reset (123) command and while allowing write access to memory (112) to receive the boot loader code image (114) written to memory (112). The boot logic also blocks commands to the memory subsystem (109) from the debug access port and turns off write access to memory (112) after allowing the boot loader code image (114) to be written. The boot logic validates the boot loader code image (114) by performing a security check and jumps to the boot loader code image (114) if it is valid, thereby allowing it to run on the programmable processor (103). The boot logic may be logic circuits, software or a combination thereof.
摘要翻译：集成电路（100）可以经由调试访问端口（105）接收引导加载程序代码（114），其中启动逻辑可操作以在可编程处理器（103）的复位（123）从调试访问端口（105），命令和来自调试访问端口的可编程处理器，同时仍然允许复位（123）命令，同时允许对存储器（112）的写访问以接收写入存储器的引导加载程序代码映像（114） 112）。引导逻辑还从调试访问端口阻止对存储器子系统（109）的命令，并且在允许写入引导加载程序代码映像（114）之后，关闭对存储器（112）的写访问。启动逻辑通过执行安全检查来验证引导加载程序代码映像（114），并且如果其有效则跳转到引导加载程序代码映像（114），从而允许其在可编程处理器（103）上运行。引导逻辑可以是逻辑电路，软件或其组合。

2. 发明申请

US20090285390A1 INTEGRATED CIRCUIT WITH SECURED SOFTWARE IMAGE AND METHOD THEREFOR 审中-公开
标题翻译：具有安全软件映像的集成电路及其方法
公开(公告)号：US20090285390A1
公开(公告)日：2009-11-19
申请号：US12122444
申请日：2008-05-16
申请人： Stefan Thomas Scherer , Denis Foley , Alwyn Dos Remedios
发明人： Stefan Thomas Scherer , Denis Foley , Alwyn Dos Remedios
IPC分类号： H04L9/06
CPC分类号： G06F21/51 , G06F21/565
摘要： The various embodiments herein disclosed include a method wherein an integrated circuit (100) may receive a code image from an external device (127), encrypt the code image using a cryptographic logic (113) with a Hardware Unique Key to create a Hardware Unique Code Image (119) where the Hardware Unique Key is inaccessible to the external device (127). The integrated circuit (100) will then store the Hardware Unique Code Image wherein the Hardware Unique Code Image is executable only after decryption using the Hardware Unique Key. The method also includes sending a command to a cryptographic logic (113) to request decryption of the Hardware Unique Code Image by the cryptographic logic (113) using the Hardware Unique Key and executing the Hardware Unique Code Image by the boot software (103) after the decryption.
摘要翻译：本文公开的各种实施例包括其中集成电路（100）可以从外部设备（127）接收代码图像的方法，使用具有硬件唯一密钥的密码逻辑（113）加密代码图像，以创建硬件唯一代码外部设备（127）无法访问硬件唯一密钥的图像（119）。然后，集成电路（100）将存储硬件唯一码图像，其中硬件唯一码图像仅在使用硬件唯一密钥进行解密之后才可执行。该方法还包括向加密逻辑（113）发送命令，以使用硬件唯一密钥通过密码逻辑（113）请求解密硬件唯一码映像，并且在引导软件（103）之后由引导软件（103）执行硬件唯一码映像解密。

3. 发明申请

US20070226456A1 System and method for employing multiple processors in a computer system 审中-公开
标题翻译：在计算机系统中采用多个处理器的系统和方法
公开(公告)号：US20070226456A1
公开(公告)日：2007-09-27
申请号：US11386026
申请日：2006-03-21
申请人： Mark Shaw , Stuart Berke , Denis Foley
发明人： Mark Shaw , Stuart Berke , Denis Foley
IPC分类号： G06F15/00
CPC分类号： G06F15/17337
摘要： There is provided a system and a method for employing multiple processors in a computer system. More specifically, there is provided a computer system comprising a first cell board including a first central processing unit, a second central processing unit, and a first data agent coupled to the first and second central processing units and configured to transmit signals from the first and second central processing units to a first crossbar circuit. There is also provided a second cell board including a third central processing unit coupled to the first central processing unit via a point-to-point data link, a fourth central processing unit, and a second data agent coupled to the third and fourth central processing units and configured to transmit signals from the third and fourth central processing units to a second crossbar circuit.
摘要翻译：提供了一种在计算机系统中采用多个处理器的系统和方法。更具体地，提供了一种计算机系统，包括第一单元板，其包括第一中央处理单元，第二中央处理单元和耦合到第一和第二中央处理单元的第一数据代理，并且被配置为从第一和第二中央处理单元第二中央处理单元连接到第一横向电路。还提供了一种第二单元板，包括经由点到点数据链路耦合到第一中央处理单元的第三中央处理单元，第四中央处理单元和耦合到第三和第四中央处理的第二数据代理单元并且被配置为将信号从第三和第四中央处理单元传送到第二交叉电路。

4. 发明授权

US06256694B1 Distributed early arbitration 失效
标题翻译：分散的早期仲裁
公开(公告)号：US06256694B1
公开(公告)日：2001-07-03
申请号：US08269251
申请日：1994-06-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F1336
CPC分类号： G06F13/36 , G06F12/0884 , G06F13/368
摘要： A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.
摘要翻译：一个指挥官模块，其耦合到包括系统总线控制请求信号并与系统总线控制请求信号之一相关联的系统总线，包括用于确定是否需要控制系统总线的装置，以及用于请求控制系统总线的装置以通过断言相关的系统总线控制请求信号来确定是否需要这样的控制。包括系统总线和耦合到系统总线的至少两个这样的指挥器模块的计算机系统以及用于仲裁以控制系统总线的装置，其中仲裁装置耦合到并且响应于系统总线控制请求信号。

5. 发明授权

US5758106A Arbitration unit which requests control of the system bus prior to determining whether such control is required 失效
标题翻译：在确定是否需要此类控制之前，要求对系统总线进行控制的仲裁单元
公开(公告)号：US5758106A
公开(公告)日：1998-05-26
申请号：US741084
申请日：1996-10-30
申请人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G06F13/368 , G06F13/36
CPC分类号： G06F13/368
摘要： A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.
摘要翻译：一种指挥官模块，包括用于确定是否需要控制系统总线的装置，用于在确定是否需要这种控制之前请求对系统总线的控制的装置，以及响应于确定装置指示系统的控制的装置公车是必需的。一种计算机系统，包括系统总线和耦合到系统总线的至少两个这样的指挥器模块，并且包括用于仲裁用于系统总线控制的装置，包括用于将系统总线的控制授权给指令器模块之一，指示控制系统总线是必需的，并且在这些指挥器模块中具有最高的仲裁优先级，还指示需要对系统总线的控制。

6. 发明授权

US5566325A Method and apparatus for adaptive memory access 失效
标题翻译：用于自适应存储器访问的方法和装置
公开(公告)号：US5566325A
公开(公告)日：1996-10-15
申请号：US269259
申请日：1994-06-30
申请人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
发明人： E. William Bruce, II , Dave Hartwell , David M. Fenwick , Denis Foley , Stephen R. Van Doren
IPC分类号： G11C7/22 , G11C8/18 , G06F12/00 , G06F1/12
CPC分类号： G11C8/18 , G11C7/22
摘要： A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.
摘要翻译：提供了一种存储器系统，其可以适应于耦合到能够以不同时钟速度运行的总线。存储器系统响应由总线速度传感器提供的信号，用于修改行地址选通（RAS），列地址选通（CAS）和写使能（WE）信号的定时。通过修改RAS，CAS和WE信号的时序，可以在能够以各种总线速度工作的系统中操作存储器，而不会遇到通常与总线速度变化相关的延迟问题。

7. 发明授权

US5537575A System for handling cache memory victim data which transfers data from cache to the interface while CPU performs a cache lookup using cache status information 失效
标题翻译：用于处理高速缓存存储器受害者数据的系统，该缓冲存储器将数据从高速缓存传送到接口，而CPU使用高速缓存状态信息执
公开(公告)号：US5537575A
公开(公告)日：1996-07-16
申请号：US268403
申请日：1994-06-30
申请人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
发明人： Denis Foley , Douglas J. Burns , Stephen R. Van Doren
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0804
摘要： A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus. In response to the command for transmitting cache memory victim data, the cache memory data which is waiting in the data interface, is transmitted from the data interface to main memory over the system bus.
摘要翻译：一种用于处理用于更新主存储器的高速缓存存储器受害数据的计算机系统中的方法和装置。本发明在具有通过根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块耦合到主存储器的计算机系统中操作。在执行了一个高速缓存存储器地址的READ的处理器中，对应于正在读取的高速缓存存储器地址的高速缓存存储器数据从高速缓冲存储器数据存储器发送到数据接口。高速缓存存储器数据在执行高速缓存存储器地址信息的READ期间被数据接口累积地接收。确定与高速缓存存储器地址相对应的高速缓存存储器数据是否为高速缓存存储器受害者。如果该确定确定它是缓存存储器受害者，则处理器通过系统总线发出用于将高速缓存存储器受害数据发送到主存储器的命令。响应于用于发送高速缓存存储器受害者数据的命令，在数据接口中等待的高速缓存存储器数据通过系统总线从数据接口发送到主存储器。

8. 发明授权

US08051345B2 Method and apparatus for securing digital information on an integrated circuit during test operating modes 有权
标题翻译：用于在测试操作模式下在集成电路上保护数字信息的方法和装置
公开(公告)号：US08051345B2
公开(公告)日：2011-11-01
申请号：US12133173
申请日：2008-06-04
申请人： Serag M. GadelRab , Bin Du , Zeeshan S. Syed , Denis Foley
发明人： Serag M. GadelRab , Bin Du , Zeeshan S. Syed , Denis Foley
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G11C7/24 , G11C29/12 , G11C29/14 , G11C2029/3202
摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.
摘要翻译：这些实施例保护IC免受测试（DFT）或其他测试模式攻击。确保存储在存储在ROM和/或PROM中的寄存器或锁存器，RAM和/或永久机密中的临时秘密。用于保护IC上的信息的一个实施例包括响应于进入测试操作模式并在接收到测试模式命令之前进入测试模式并重置每个寄存器。集成电路实施例包括测试控制逻辑，其可操作以将集成电路配置为测试模式并且在测试模式期间控制集成电路，一组寄存器以及耦合到测试控制逻辑的功能复位控制器一组寄存器，用于从测试控制逻辑接收复位命令，并响应于进入测试模式的命令向该组寄存器提供复位命令。

9. 发明申请

US20090307502A1 METHOD AND APPARATUS FOR SECURING DIGITAL INFORMATION ON AN INTEGRATED CIRCUIT READ ONLY MEMORY DURING TEST OPERATING MODES 有权
标题翻译：一体化电路数字信息保护方法与装置在测试运行模式下只读存储器
公开(公告)号：US20090307502A1
公开(公告)日：2009-12-10
申请号：US12133185
申请日：2008-06-04
申请人： Serag M. GadelRab , Bin Du , Zeeshan S. Syed , Denis Foley
发明人： Serag M. GadelRab , Bin Du , Zeeshan S. Syed , Denis Foley
IPC分类号： H04L9/06
CPC分类号： G01R33/093 , B82Y25/00 , G01R31/318536 , G01R31/318541
摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.
摘要翻译：这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 ROM或PROM中的秘密是安全的。用于保护IC上的信息的一个实施例包括接收ROM读取命令，响应于接收到ROM读取命令将数据从多个ROM地址位置写入加密逻辑，并将加密逻辑的加密逻辑输出写入测试控制逻辑，加密逻辑输出表示来自多个ROM地址位置的数据。将数据从多个ROM地址位置写入加密逻辑还可以包括响应于ROM读命令将来自多个ROM地址位置的数据写入多输入移位寄存器（MISR），以及将MISR输出写入测试控制逻辑，MISR输出表示来自多个ROM地址位置的数据。

10. 发明授权

US5625805A Clock architecture for synchronous system bus which regulates and adjusts clock skew 失效
标题翻译：同步系统总线的时钟架构，可调节和调整时钟偏移
公开(公告)号：US5625805A
公开(公告)日：1997-04-29
申请号：US269223
申请日：1994-06-30
申请人： David M. Fenwick , Daniel Wissell , Richard Watson , Denis Foley
发明人： David M. Fenwick , Daniel Wissell , Richard Watson , Denis Foley
IPC分类号： G06F1/10
CPC分类号： G06F1/10
摘要： A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.
摘要翻译：描述了同步计算机系统。该系统是具有总线系统时钟和每个处理器的处理器时钟的多处理器系统。该系统包括同步计算机系统总线和耦合到同步总线的多个电路模块，其中至少两个模块具有至少一个处理器，处理器模块具有至少一个处理器，其与另一个处理器异步运行处理器，而处理器模块与系统总线同步。该系统还包括用于提供对应的多个时钟信号的时钟发生器装置和耦合在所述时钟发生装置和所述多个模块之间的多个导体。每个所述导体具有基本上相同的电路径长度的电路径，其中每个所述模块还包括耦合到所述导体中的相应一个导体并设置在所述模块上的装置，用于调节和调整所述模块上的时钟信号之间的偏差。

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