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31. 发明授权

US09715413B2 Execution state analysis for assigning tasks to streaming multiprocessors 有权
公开(公告)号：US09715413B2
公开(公告)日：2017-07-25
申请号：US13353155
申请日：2012-01-18
申请人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
发明人： Karim M. Abdalla , Lacky V. Shah , Jerome F. Duluk, Jr. , Timothy John Purcell , Tanmoy Mandal , Gentaro Hirota
IPC分类号： G06F9/46 , G06F13/00 , G06F9/50
CPC分类号： G06F9/505 , G06F2209/503
摘要： One embodiment of the present invention sets forth a technique for selecting a first processor included in a plurality of processors to receive work related to a compute task. The technique involves analyzing state data of each processor in the plurality of processors to identify one or more processors that have already been assigned one compute task and are eligible to receive work related to the one compute task, receiving, from each of the one or more processors identified as eligible, an availability value that indicates the capacity of the processor to receive new work, selecting a first processor to receive work related to the one compute task based on the availability values received from the one or more processors, and issuing, to the first processor via a cooperative thread array (CTA), the work related to the one compute task.

32. 发明授权

US09436969B2 Time slice processing of tessellation and geometry shaders 有权
标题翻译：镶嵌和几何着色器的时间片处理
公开(公告)号：US09436969B2
公开(公告)日：2016-09-06
申请号：US13208256
申请日：2011-08-11
申请人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
发明人： Ziyad S. Hakura , Emmett M. Kilgariff , Dale L. Kirkland , Johnny S. Rhoades , Cynthia Ann Edgeworth Allison , Karim M. Abdalla
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： One embodiment of the present invention sets forth a technique for redistributing geometric primitives generated by tessellation and geometry shaders for processing by multiple graphics pipelines. Geometric primitives that are generated in a first processing cycle are collected and redistributed more evenly and in smaller tasks to the multiple graphics pipelines for vertex processing in a second processing cycle. The smaller tasks do not exceed the resource limits of a graphics pipeline and the per-vertex processing workloads of the graphics pipelines in the second cycle are balanced and make full use of resources. Therefore, the performance of the tessellation and geometry shaders is improved.
摘要翻译：本发明的一个实施例提出了一种用于重新分配由镶嵌和几何着色器生成的几何图元以用于由多个图形管线进行处理的技术。在第一个处理周期中生成的几何图元在第二个处理周期中被收集并且更均匀地并且在更小的任务中重新分布到用于顶点处理的多个图形流水线。较小的任务不超过图形管道的资源限制，并且第二周期中的图形管道的每顶点处理工作负载平衡并充分利用资源。因此，纹理和几何着色器的性能得到改善。

33. 发明申请

US20120176377A1 BLOCK LINEAR MEMORY ORDERING OF TEXTURE DATA TECHNIQUES 有权
标题翻译：块纹线数据技术的线性记忆订单
公开(公告)号：US20120176377A1
公开(公告)日：2012-07-12
申请号：US13422498
申请日：2012-03-16
申请人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
发明人： Walter E. Donovan , Emmett M. Kilgariff , Karim M. Abdalla , Joel J. McCormack
IPC分类号： G06T15/04 , G06T11/40
CPC分类号： G06T15/04 , G06T1/60
摘要： A method of organizing memory for storage of texture data, in accordance with one embodiment of the invention, includes accessing a size of a mipmap level of a texture map. A block dimension may be determined based on the size of the mipmap level. A memory space (e.g., computer-readable medium) may be logically divided into a plurality of whole number of blocks of variable dimension. The dimension of the blocks is measured in units of gobs and each gob is of a fixed dimension of bytes. A mipmap level of a texture map may be stored in the memory space. A texel coordinate of said mipmap level may be converted into a byte address of the memory space by determining a gob address of a gob in which the texel coordinate resides and determining a byte address within the particular gob.
摘要翻译：根据本发明的一个实施例的组织用于存储纹理数据的存储器的方法包括访问纹理映射的mipmap级别的大小。可以基于mipmap级别的大小来确定块维度。存储器空间（例如，计算机可读介质）可以在逻辑上被划分为多个整数个可变维度的块。块的尺寸以料滴为单位进行测量，每个料滴的固定尺寸为字节。纹理映射的mipmap级别可以存储在存储器空间中。所述mipmap级别的纹理坐标可以通过确定纹理坐标所驻留的料滴的料滴地址并确定特定料滴中的字节地址来转换为存储器空间的字节地址。

34. 发明授权

US07425966B2 Pixel center position displacement 有权
标题翻译：像素中心位置位移
公开(公告)号：US07425966B2
公开(公告)日：2008-09-16
申请号：US10960857
申请日：2004-10-07
申请人： Rui M. Bastos , Michael J. M. Toksvig , Karim M. Abdalla
发明人： Rui M. Bastos , Michael J. M. Toksvig , Karim M. Abdalla
IPC分类号： G09G5/00 , G06T11/20 , G06T15/00 , G06K9/36 , G00K9/40
CPC分类号： G06T3/40
摘要： A pixel center position that is not covered by a primitive covering a portion of the pixel is displaced to lie within a fragment formed by the intersection of the primitive and the pixel. X,y coordinates of a pixel center are adjusted to displace the pixel center position to lie within the fragment, affecting actual texture map coordinates or barycentric weights. Alternatively, a centroid sub-pixel sample position is determined based on coverage data for the pixel and a multisample mode. The centroid sub-pixel sample position is used to compute pixel or sub-pixel parameters for the fragment.
摘要翻译：未被覆盖像素的一部分的原图覆盖的像素中心位置被移位以位于由图元和像素的交点形成的片段内。调整像素中心的X，Y坐标以使像素中心位置位于片段内，影响实际纹理图坐标或重心权重。或者，基于像素的覆盖数据和多采样模式来确定质心子像素采样位置。质心子像素采样位置用于计算片段的像素或子像素参数。

35. 发明授权

US07218291B2 Increased scalability in the fragment shading pipeline 有权
标题翻译：增加片段着色管道中的可扩展性
公开(公告)号：US07218291B2
公开(公告)日：2007-05-15
申请号：US10940070
申请日：2004-09-13
申请人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
发明人： Karim M. Abdalla , Emmett M. Kilgariff , Rui M. Bastos
IPC分类号： G09G1/14 , G06T15/50
CPC分类号： G06T11/40 , G06T15/005 , G06T15/50 , G06T15/80
摘要： A fragment processor includes a fragment shader distributor, a fragment shader collector, and a plurality of fragment shader pipelines. Each fragment shader pipeline executes a fragment shader program on a segment of fragments. The plurality of fragment shader pipelines operate in parallel, executing the same or different fragment shader programs. The fragment shader distributor receives a stream of fragments from a rasterization unit and dispatches a portion of the stream of fragments to a selected fragment shader pipeline until the capacity of the selected fragment shader pipeline is reached. The fragment shader distributor then selects another fragment shader pipeline. The capacity of each of the fragment shader pipelines is limited by several different resources. As the fragment shader distributor dispatches fragments, it tracks the remaining available resources of the selected fragment shader pipeline. A fragment shader collector retrieves processed fragments from the plurality of fragment shader pipelines.
摘要翻译：片段处理器包括片段着色器分配器，片段着色器收集器和多个片段着色器管线。每个片段着色器流水线在片段片段上执行片段着色器程序。多个片段着色器管线并行操作，执行相同或不同的片段着色器程序。片段着色器分配器从光栅化单元接收片段流，并将片段流的一部分分派到所选择的片段着色器管线，直到达到所选片段着色器管线的容量。片段着色器分配器然后选择另一个片段着色器管道。每个片段着色器管道的容量受到几个不同的资源的限制。当片段着色器分配器调度片段时，它会跟踪所选片段着色器管道的剩余可用资源。片段着色器收集器从多个片段着色器管道中检索已处理的片段。

36. 发明授权

US6154794A Upstream situated apparatus and method within a computer system for controlling data flow to a downstream situated input/output unit 失效
标题翻译：用于控制到下游位置的输入/输出单元的数据流的计算机系统内的上游设备和方法
公开(公告)号：US6154794A
公开(公告)日：2000-11-28
申请号：US716951
申请日：1996-09-08
申请人： Karim M. Abdalla , Kianoosh Naghshineh , James E. Tornes , Daniel Yau
发明人： Karim M. Abdalla , Kianoosh Naghshineh , James E. Tornes , Daniel Yau
IPC分类号： G06F3/14 , G06F13/14 , G06F13/20
CPC分类号： G06F3/14
摘要： A method and apparatus for controlling the flow of information (e.g., graphics primitives, display data, etc.) to an input/output unit within a computer controlled graphics system. The system includes a processor having a first-in-first-out (FIFO) buffer, a separate input/output unit with its FIFO buffer, and a number of intermediate devices (with FIFO buffers) coupled between the input/output unit and the processor for moving input/output data from the processor to the input/output unit. Mechanisms are placed within an intermediate device, very close to the processor, which maintain an accounting of the number of input/output data sent to the input/output unit, but not yet cleared from the input/output unit's buffer. These mechanisms regulate data flow to the input/output unit. By placing these mechanisms close to the processor, rather than within the input/output unit, the system allows a larger portion of the input/output unit's buffer to be utilized for storing input/output data before a processor suspend or interrupt is required. This leads to increased input/output data throughput between the processor and the input/output unit by reducing processor interrupts. The system also includes an efficiently invoked timer mechanism for temporarily suspending the processor from transmitting stores to the input/output unit when the input/output unit and/or the intermediate devices are congested. The processor is not interrupted by an interrupt request until after the timer mechanism times out, allowing the system an opportunity to clear its congestion before a lengthily invoked interrupt is required.
摘要翻译：一种用于控制计算机控制的图形系统内的输入/输出单元的信息流（例如，图形基元，显示数据等）的方法和装置。该系统包括具有先进先出（FIFO）缓冲器，具有其FIFO缓冲器的单独输入/输出单元和耦合在输入/输出单元与多个FIFO缓冲器之间的多个中间设备（具有FIFO缓冲器）处理器，用于将输入/输出数据从处理器移动到输入/输出单元。机构位于非常接近处理器的中间设备内，其维持对输入/输出单元发送的输入/输出数据的数量的记账，但尚未从输入/输出单元的缓冲器中清除。这些机制调节到输入/输出单元的数据流。通过将这些机制放置在处理器附近，而不是在输入/输出单元内，系统允许输入/输出单元的缓冲区的较大部分用于在处理器挂起或中断之前存储输入/输出数据。这导致通过减少处理器中断来增加处理器和输入/输出单元之间的输入/输出数据吞吐量。当输入/输出单元和/或中间设备拥塞时，系统还包括有效地调用定时器机制，用于暂时将处理器从发送存储发送到输入/输出单元。在定时器机制超时之后，处理器不会被中断请求中断，从而允许系统在需要长时间调用中断之前清除其拥塞。

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