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31. 发明申请

US20090175076A1 Memory device and method for estimating characteristics of multi-bit cell 有权
标题翻译：用于估计多位单元特性的存储器件和方法
公开(公告)号：US20090175076A1
公开(公告)日：2009-07-09
申请号：US12213657
申请日：2008-06-23
申请人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
发明人： Kyoung Lae Cho , Seung-Hwan Song , Yoon Dong Park , Jun Jin Kong , Jae-Hong Kim
IPC分类号： G11C16/00 , G11C7/00
CPC分类号： G11C11/5628 , G11C16/32 , G11C16/349 , G11C29/00 , G11C2211/5634
摘要： Memory devices and/or methods that may estimate characteristics of multi-bit cell are provided. A memory device may include: a multi-bit cell array; a monitoring unit to extract a threshold voltage change over time value for reference threshold voltage states selected from a plurality of threshold voltage states corresponding to data stored in the multi-bit cell array; and an estimation unit to estimate a threshold voltage change over time values for the plurality of threshold voltage states based on the extracted threshold voltage change. Through this, it is possible to monitor a change over time of threshold voltages of a memory cell.
摘要翻译：提供了可以估计多位单元特性的存储器件和/或方法。存储器设备可以包括：多位单元阵列; 监测单元，用于提取从对应于存储在多位单元阵列中的数据的多个阈值电压状态中选择的参考阈值电压状态的时间值的阈值电压变化; 以及估计单元，用于基于所提取的阈值电压变化来估计所述多个阈值电压状态的时间值的阈值电压变化。由此，可以监视存储单元的阈值电压随时间的变化。

32. 发明申请

US20090103359A1 Apparatus and method of multi-bit programming 有权
标题翻译：多位编程的装置和方法
公开(公告)号：US20090103359A1
公开(公告)日：2009-04-23
申请号：US12073101
申请日：2008-02-29
申请人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
发明人： Seung-Hwan SONG , Kyoung Lae Cho , Heeseok Eun , Dong Hyuk Chae , Jun Jin Kong , Sung Chung Park
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C2211/5621
摘要： Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may comprise: a multi-bit cell array that includes a first multi-bit cell and a second multi-bit cell; a programming unit for programming first data in the first multi-bit cell, and programming second data in the second multi-bit cell; and a verification unit for verifying whether the first data is programmed in the first multi-bit cell using a first verification voltage, and verifying whether the second data is programmed in the second multi-bit cell using a second verification voltage. The multi-bit programming apparatus may generate better threshold voltage distributions in a multi-bit cell memory.
摘要翻译：提供了多位编程设备和/或方法。多比特编程装置可以包括：包括第一多比特小区和第二多比特小区的多比特单元阵列; 编程单元，用于对第一多位单元中的第一数据进行编程，以及编程第二多位单元中的第二数据; 以及验证单元，用于使用第一验证电压来验证第一数据是否被编程在第一多位单元中，以及使用第二验证电压来验证第二数据是否被编程在第二多位单元中。多比特编程装置可以在多比特单元存储器中产生更好的阈值电压分布。

33. 发明申请

US20090091991A1 Apparatuses and methods for multi-bit programming 失效
标题翻译：多位编程的设备和方法
公开(公告)号：US20090091991A1
公开(公告)日：2009-04-09
申请号：US12073100
申请日：2008-02-29
申请人： Kyoung Lae Cho , Jun Jin Kong , Jong Han Kim , Seung Hoon Lee , Young Hwan Lee , Sung-Jae Byun , Ju Hee Park
发明人： Kyoung Lae Cho , Jun Jin Kong , Jong Han Kim , Seung Hoon Lee , Young Hwan Lee , Sung-Jae Byun , Ju Hee Park
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C2211/5647
摘要： Multi-bit programming apparatuses and methods are provided. A multi-bit programming apparatus includes a page buffer configured to store first data of the page programming operation, an input control unit configured to determine whether to invert the first data based on a number of bits having a first value and a number of bits having a second value. The input control unit is further configured to invert the first data to generate second data if the number of bits having a first value is greater than the number of bits having a second value and store the second data in the page buffer. The multi-bit programming apparatus further includes a page programming unit configured to program the second data stored in the page buffer in at least one multi-bit cell.
摘要翻译：提供了多位编程设备和方法。一种多位编程装置，包括：页缓冲器，被配置为存储页编程操作的第一数据;输入控制单元，被配置为基于具有第一值的比特数和具有多个比特的比特数来确定是否反转第一数据第二个值。输入控制单元还被配置为如果具有第一值的比特数大于具有第二值的比特数，并且将第二数据存储在页面缓冲器中，则反转第一数据以产生第二数据。该多位编程装置还包括：页面编程单元，被配置为在至少一个多位单元中对存储在页缓冲器中的第二数据进行编程。

34. 发明申请

US20080163023A1 ECC controller for use in flash memory device and memory system including the same 有权
标题翻译：用于闪存器件的ECC控制器和包括其的存储器系统
公开(公告)号：US20080163023A1
公开(公告)日：2008-07-03
申请号：US11785719
申请日：2007-04-19
申请人： Si-Hoon Hong , Yun-Tae Lee , Jun-Jin Kong
发明人： Si-Hoon Hong , Yun-Tae Lee , Jun-Jin Kong
IPC分类号： H03M13/00
CPC分类号： H03M13/2945 , G06F11/1072 , H03M13/09 , H03M13/136 , H03M13/1505 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/29 , H03M13/2906
摘要： An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device.
摘要翻译：存储M位数据（M为等于或大于2的正整数）的闪速存储器件的ECC（纠错码）控制器包括从程序数据生成第一ECC数据的第一ECC块，根据第一纠错方法存储在闪速存储装置中的第二ECC数据和根据第二纠错方法从第一ECC数据和从第一ECC块输出的程序数据生成第二ECC数据的第二ECC块，，第一ECC数据和第二ECC数据被存储在闪存设备中。

35. 发明申请

US20080158238A1 FORMAT CONVERSION APPARATUS FROM BAND INTERLEAVE FORMAT TO BAND SEPARATE FORMAT 有权
标题翻译：格式转换装置从条带间隔格式到单独格式
公开(公告)号：US20080158238A1
公开(公告)日：2008-07-03
申请号：US11769319
申请日：2007-06-27
申请人： Jong Myon KIM , Jun Jin KONG , Jeongwook KIM , Suk Jin KIM , Soojung RYU , Kyoung June MIN , Dong-Hoon YOO , Dong Kwan SUH , Yeon Gon CHO
发明人： Jong Myon KIM , Jun Jin KONG , Jeongwook KIM , Suk Jin KIM , Soojung RYU , Kyoung June MIN , Dong-Hoon YOO , Dong Kwan SUH , Yeon Gon CHO
IPC分类号： G09G5/36 , G06F12/00 , G06T1/60
CPC分类号： G06T3/606
摘要： A format conversion apparatus which converts image data of a band interleave format into image data of a band separate format is provided. The apparatus includes a memory which stores image data of a band interleave format; and a converting module which reads the memory by increasing a read address of the memory for each stride, and converts the image data of the band interleave format into image data of a band separate format.
摘要翻译：提供将频带交织格式的图像数据转换成带分离格式的图像数据的格式转换装置。该装置包括：存储器，其存储频带交织格式的图像数据; 以及转换模块，其通过增加每个步幅的存储器的读取地址来读取存储器，并将频带交织格式的图像数据转换为带分离格式的图像数据。

36. 发明申请

US20080151621A1 Multi-level cell memory devices and methods of storing data in and reading data from the memory devices 有权
标题翻译：多级单元存储器件以及将数据存储在存储器件中并从其读取数据的方法
公开(公告)号：US20080151621A1
公开(公告)日：2008-06-26
申请号：US11802656
申请日：2007-05-24
申请人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
发明人： Jun Jin Kong , Sung Chung Park , Dong Ku Kang , Young Hwan Lee , Si Hoon Hong , Jae Woong Hyun
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/0483
摘要： A multi-level cell (MLC) memory device may include ‘a’ number of m-bit MLC memory cells; an encoder that encodes ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream; and a signal mapping module that applies pulses to the MLC memory cells in order to write the encoded bit stream in the MLC memory cells. In the device, ‘a’ and ‘m’ may be integers greater than or equal to 2, ‘k’ and ‘n’ may be integers greater than or equal to 1, and ‘n’ may be greater than ‘k’. A method of storing data in the device may include encoding ‘k’ bits of data at a code rate of k/n to generate an encoded bit stream. A method of reading data from the device may include decoding ‘n’ bits of data at a code rate of n/k to generate a decoded bit stream.
摘要翻译：多级单元（MLC）存储器件可以包括“a”个m位MLC存储器单元; 编码器，其以k / n的码率对“k”位数据进行编码，以产生编码比特流; 以及信号映射模块，其向MLC存储器单元施加脉冲以便将编码比特流写入MLC存储器单元。在设备中，'a'和'm'可以是大于或等于2的整数，'k'和'n'可以是大于或等于1的整数，'n'可能大于'k'。在设备中存储数据的方法可以包括以k / n的码率对'k'位数据进行编码，以产生编码比特流。从设备读取数据的方法可以包括以n / k的码率对'n'比特的数据进行解码，以产生解码比特流。

37. 发明申请

US20080137414A1 Multi-level cell memory device and method thereof 有权
标题翻译：多级单元存储装置及其方法
公开(公告)号：US20080137414A1
公开(公告)日：2008-06-12
申请号：US11808173
申请日：2007-06-07
申请人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
发明人： Sung Chung Park , Jun Jin Kong , Young Hwan Lee , Dong Ku Kang
IPC分类号： G11C7/10
CPC分类号： G11C11/5621 , G11C7/1006 , G11C29/00
摘要： A Multi-Level Cell (MLC) memory device and method thereof are provided. The example MLC memory device may be configured to perform data operations, and may include an MLC memory cell, a first coding device performing a first coding function, the first coding function being one of an encoding function and a decoding function, a second coding device performing a second coding function, the second coding function being one of an encoding function and a decoding function and a signal module configured to perform at least one of instructing the MLC memory cell to store data output by the second coding device if the first and second coding functions are encoding functions, and generating a demapped bit stream based on data retrieved from the MLC memory cell if the first and second coding functions are decoding functions.
摘要翻译：提供了一种多级单元（MLC）存储器件及其方法。示例MLC存储器件可以被配置为执行数据操作，并且可以包括MLC存储器单元，执行第一编码功能的第一编码装置，作为编码功能和解码功能之一的第一编码功能，第二编码装置执行第二编码功能，所述第二编码功能是编码功能和解码功能之一;以及信号模块，被配置为执行指令所述MLC存储器单元存储由所述第二编码装置输出的数据中的至少一个，如果所述第一和第二编码功能编码功能是编码功能，并且如果第一和第二编码功能是解码功能，则基于从MLC存储器单元检索的数据来生成解映射比特流。

38. 发明申请

US20080056392A1 Dual carrier modulation (DCM) demapper and DCM demapping method 有权
标题翻译：双载波调制（DCM）解映射器和DCM解映射方法
公开(公告)号：US20080056392A1
公开(公告)日：2008-03-06
申请号：US11704907
申请日：2007-02-12
申请人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
发明人： Sung Chung Park , Yun Young Kim , Jun Jin Kong , Jae Ho Roh
IPC分类号： H04K1/10 , H03D1/00
CPC分类号： H04L27/2649 , H04L25/022 , H04L25/067 , H04L27/3416
摘要： A DCM demapper and a DCM demapping method are provided. The DCM demapper includes: a basic signal generation unit generating a plurality of basic signals using a signal and channel information of two subcarriers; a soft decision generation unit generating a plurality of soft decisions using the plurality of basic signals; and a soft decision selection unit selecting a soft decision corresponding to each bit of the two subcarriers among the generated soft decisions.
摘要翻译：提供DCM解映射器和DCM解映射方法。 DCM解映射器包括：使用信号和两个子载波的信道信息生成多个基本信号的基本信号生成单元; 软判决生成单元，使用所述多个基本信号生成多个软判决; 以及软判决选择单元，在所生成的软决策中选择与所述两个子载波的每个比特相对应的软判决。

39. 发明授权

US06799296B2 Viterbi detector for optical disk system 失效
标题翻译：维特比检测器用于光盘系统
公开(公告)号：US06799296B2
公开(公告)日：2004-09-28
申请号：US09985122
申请日：2001-11-01
申请人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
发明人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
IPC分类号： H03M1300
CPC分类号： H03M13/6343 , G11B20/10009 , H03M13/3961 , H03M13/41 , H03M13/4107
摘要： A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.
摘要翻译：一种用于光盘系统的高速维特比检测器，包括用于产生主时钟频率三分之一的辅助时钟的分频单元，用于计算多个分支度量中的每一个的分支量度计算单元，平行转换单元，用于以3个状态位为单位输出主时钟频率的每个分支度量，用于添加分支度量和先前存储的状态度量的加法/比较/选择单元，并用于比较加法结果以选择和输出将附加结果的最小值作为新的状态度量，并且在辅助时钟频率处输出用于存储路径选择信号并用于输出与路径选择信号相对应的并行数据的路径存储器的相应路径选择信号，辅助时钟频率以及用于将路径存储器输出转换为串行数据的并行到串行转换单元。

40. 发明授权

US6029268A Quality calculator apparatus for use with Viterbi-decoded data using zero-state metrics 失效
标题翻译：使用零状态度量的维特比解码数据使用的质量计算器装置
公开(公告)号：US6029268A
公开(公告)日：2000-02-22
申请号：US839
申请日：1997-12-30
申请人： Jun-jin Kong , Sung-han Choi
发明人： Jun-jin Kong , Sung-han Choi
IPC分类号： H04L29/14 , H03M13/23 , H03M13/35 , H03M13/41 , G06F11/10
CPC分类号： H03M13/6569 , H03M13/35 , H03M13/4107 , H03M13/413
摘要： A quality calculator apparatus for Viterbi-decoded data using zero-state metrics. The quality calculator for the Viterbi-decoded data includes: a Viterbi decoder which outputs zero-state metrics of input demodulated data according to the four possible transmission rates of FULL, HALF, QUARTER and 1/8; a register which stores respective zero-state metrics output from the Viterbi decoder; and a quality evaluation unit which reads the zero-state metrics stored in the register to evaluate the Viterbi-decoded data based on the zero-state metrics and which determines the actual transmission rate to be the one among the possible transmission rates which has the least zero-state metrics. The zero-state metrics of the demodulated data input to the Viterbi decoder are used as a quality evaluation parameter so that the quality evaluation can be correctly achieved to avoid errors in determining of the transmission rate, as compared to a quality calculator using a bit error ratio as the quality evaluation parameter.
摘要翻译：一种使用零状态度量的维特比解码数据的质量计算器装置。用于维特比解码数据的质量计算器包括：维特比解码器，其根据FULL，HALF，QUARTER和+ E，fra 1/8 + EE的四种可能的传输速率输出输入解调数据的零状态度量; 存储从维特比解码器输出的相应的零状态度量的寄存器; 以及质量评估单元，其读取存储在所述寄存器中的零状态度量，以基于所述零状态量度来评估所述维特比解码数据，并且将所述实际传输速率确定为所述可能传输速率中的最小传输速率零状态指标。将输入到维特比解码器的解调数据的零状态量度用作质量评估参数，以便与使用位错误的质量计算器相比，可以正确地实现质量评估以避免确定传输速率的错误比例作为质量评估参数。

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