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1. 发明授权

US06799296B2 Viterbi detector for optical disk system 失效
标题翻译：维特比检测器用于光盘系统
公开(公告)号：US06799296B2
公开(公告)日：2004-09-28
申请号：US09985122
申请日：2001-11-01
申请人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
发明人： Jun-jin Kong , Sung-han Choi , Jae-wook Lee
IPC分类号： H03M1300
CPC分类号： H03M13/6343 , G11B20/10009 , H03M13/3961 , H03M13/41 , H03M13/4107
摘要： A high speed Viterbi detector for an optical disk system, includes a frequency dividing unit for generating an auxiliary clock at one-third of the main clock frequency, a branch metric calculation unit for calculating each of a plurality of branch metrics, a serial-to-parallel converting unit for outputting each of the branch metrics at the main clock frequency in units of 3 state bits, an addition/comparison/selection unit for adding the branch metrics and previously stored state metrics and for comparing the addition results to select and output the minimum of the addition results as a new state metric, and for outputting a corresponding path selection signal, at the auxiliary clock frequency, a path memory for storing the path selection signal and for outputting parallel data corresponding to the path selection signal, at the auxiliary clock frequency, and a parallel-to-serial converting unit for converting the path memory output into serial data.
摘要翻译：一种用于光盘系统的高速维特比检测器，包括用于产生主时钟频率三分之一的辅助时钟的分频单元，用于计算多个分支度量中的每一个的分支量度计算单元，平行转换单元，用于以3个状态位为单位输出主时钟频率的每个分支度量，用于添加分支度量和先前存储的状态度量的加法/比较/选择单元，并用于比较加法结果以选择和输出将附加结果的最小值作为新的状态度量，并且在辅助时钟频率处输出用于存储路径选择信号并用于输出与路径选择信号相对应的并行数据的路径存储器的相应路径选择信号，辅助时钟频率以及用于将路径存储器输出转换为串行数据的并行到串行转换单元。

2. 发明授权

US6029268A Quality calculator apparatus for use with Viterbi-decoded data using zero-state metrics 失效
标题翻译：使用零状态度量的维特比解码数据使用的质量计算器装置
公开(公告)号：US6029268A
公开(公告)日：2000-02-22
申请号：US839
申请日：1997-12-30
申请人： Jun-jin Kong , Sung-han Choi
发明人： Jun-jin Kong , Sung-han Choi
IPC分类号： H04L29/14 , H03M13/23 , H03M13/35 , H03M13/41 , G06F11/10
CPC分类号： H03M13/6569 , H03M13/35 , H03M13/4107 , H03M13/413
摘要： A quality calculator apparatus for Viterbi-decoded data using zero-state metrics. The quality calculator for the Viterbi-decoded data includes: a Viterbi decoder which outputs zero-state metrics of input demodulated data according to the four possible transmission rates of FULL, HALF, QUARTER and 1/8; a register which stores respective zero-state metrics output from the Viterbi decoder; and a quality evaluation unit which reads the zero-state metrics stored in the register to evaluate the Viterbi-decoded data based on the zero-state metrics and which determines the actual transmission rate to be the one among the possible transmission rates which has the least zero-state metrics. The zero-state metrics of the demodulated data input to the Viterbi decoder are used as a quality evaluation parameter so that the quality evaluation can be correctly achieved to avoid errors in determining of the transmission rate, as compared to a quality calculator using a bit error ratio as the quality evaluation parameter.
摘要翻译：一种使用零状态度量的维特比解码数据的质量计算器装置。用于维特比解码数据的质量计算器包括：维特比解码器，其根据FULL，HALF，QUARTER和+ E，fra 1/8 + EE的四种可能的传输速率输出输入解调数据的零状态度量; 存储从维特比解码器输出的相应的零状态度量的寄存器; 以及质量评估单元，其读取存储在所述寄存器中的零状态度量，以基于所述零状态量度来评估所述维特比解码数据，并且将所述实际传输速率确定为所述可能传输速率中的最小传输速率零状态指标。将输入到维特比解码器的解调数据的零状态量度用作质量评估参数，以便与使用位错误的质量计算器相比，可以正确地实现质量评估以避免确定传输速率的错误比例作为质量评估参数。

3. 发明授权

US06820232B2 Device and method for detecting errors in CRC code having reverse ordered parity bits 失效
标题翻译：用于检测具有反向有序奇偶校验位的CRC码中的错误的装置和方法
公开(公告)号：US06820232B2
公开(公告)日：2004-11-16
申请号：US09905995
申请日：2001-07-17
申请人： Jae-hong Kim , Jun-jin Kong , Sung-han Choi
发明人： Jae-hong Kim , Jun-jin Kong , Sung-han Choi
IPC分类号： H03M1300
CPC分类号： H03M13/09
摘要： A device for detecting in a receiver whether any transmission errors have occurred in the received CRC code, in a case that a transmitter transmits the CRC code created by sequencing the parity bits, which are generated using the generator polynomial, in the reverse order and appending them to the message bits. The device comprises a division unit for dividing the message bits by the parity bit generator polynomial to form the remainder, a comparison unit for bitwise comparing the remainder bits with the reverse ordered parity bits, and a decision unit for deciding whether transmission errors have occurred in the CRC code based on the results of the comparison unit. According to the present invention, the transmission errors in the received CRC code are effectively detected, when the CRC code includes the parity bits sequenced in the reverse order, unlike the conventional normal order.
摘要翻译：在接收到的CRC码中检测出发送错误是否发生的发送装置，在发送方通过使用生成多项式生成的奇偶校验位进行排序创建的CRC码的情况下，以相反的顺序进行检测，并附加他们到消息位。该装置包括：分割单元，用于将消息比特除以奇偶校验位生成多项式以形成余数;比较单元，用于将余数比特与反向有序奇偶校验比特进行比较;以及判定单元，用于判定是否发生了传输错误基于比较单元结果的CRC码。根据本发明，与传统的正常顺序不同，当CRC码包括以相反顺序排列的奇偶校验位时，有效地检测出接收的CRC码中的传输错误。

4. 发明授权

US06317472B1 Viterbi decoder 失效
标题翻译：维特比解码器
公开(公告)号：US06317472B1
公开(公告)日：2001-11-13
申请号：US09129900
申请日：1998-08-06
申请人： Sung-han Choi , Jun-jin Kong
发明人： Sung-han Choi , Jun-jin Kong
IPC分类号： H03D100
CPC分类号： H03M13/6505 , H03M13/3961 , H03M13/4107
摘要： An apparatus for providing and storing a state metric which is used for an add-compare-select (ACS) operation in a Viterbi decoder using a number of ACS units in order to enhance decoding speed. A state metric memory in Viterbi decoder uses a two-port memory, in which a memory bank for reading and writing a state metric of a first half among the N state metrics generated in a ACS unit and two memory banks for alternately reading and writing the state metric of the second half whenever a codeword is input, are incorporated into a single memory. As a result, the storage capacity for storing the state metrics can be greatly reduced as compared to a conventional apparatus.
摘要翻译：一种用于提供和存储用于使用多个ACS单元的维特比解码器中的加法比较选择（ACS）操作的状态度量以提高解码速度的装置。维特比解码器中的状态度量存储器使用双端口存储器，其中存储器组用于读取和写入在ACS单元中生成的N个状态度量中的前半部分的状态度量，以及用于交替读取和写入每当输入码字时，第二半的状态度量被并入到单个存储器中。结果，与常规装置相比，用于存储状态度量的存储容量可以大大降低。

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